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SubjectRe: readX/writeX semantic and ordering
Gabriel Paubert wrote:
> I still don't see why they would want to execute the write to the device
> register before the earlier stores enters the coherent memory domain. The
> implementation complexity is probably not worth the performance gain.

They might one day have separate store buffers for different storage
domains, to support a different cache coherency protocol for example
without the complexity of having to couple the dependencies of uncached
writes with the dependencies of cached writes.

Basically, relaxing the rules /might/ make the implementation easier.
No-one knows until the next chip is implemented.

-- Jamie

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