Messages in this thread | | | Date | Tue, 2 Nov 1999 13:43:32 +0100 | From | Jamie Lokier <> | Subject | Re: Perform minimal RAM test at boot |
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Richard B. Johnson wrote: > Yes. Note that I write only one longword, then force new data onto > the bus by pushing/popping. They I read back. The cache is not going > to be loaded/reloaded from a single longword access.
I know this is true on Pentiums, but is it true on P6 class machines? I would expect the `not [ebx]' to prefetch an entire cache line (possible from nonexistent memory), and the push/pop would not force anything onto the bus.
On a P6, even a locked memory operation does not necessarily cause bus activity.
Perhaps `wbinvd' is required. The Intel manual says: "Write back and flush internal caches; initiate write-back and flush of external caches".
-- Jamie
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