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Subject[PATCH] cache detection for AMD K5, K6, K6-2, K6-III

Hello,

the attached patches add support for AMD K5, K6, K6-2, K6-III
detection of cache size.

the patches are agains 2.2.14pre6 and 2.3.28

after patch (2.3.28):

[cata@Cnn]:~::$ cat /proc/cpuinfo | grep cache
cache size : 64 KB
[cata@Cnn]:~::$ dmesg | grep CPU
Initializing CPU#0
CPU: L1 I Cache: 32K L1 D Cache: 32K
CPU: AMD AMD-K6(tm) 3D processor stepping 0c


bye

--
Catalin Muresan
CODEC Electronic Products
Internet Services Department
1594311.45 1428170.81
--- linux-2.2.14pre6-clean/arch/i386/kernel/setup.c Wed Nov 17 16:19:03 1999
+++ linux-2.2.14pre6/arch/i386/kernel/setup.c Wed Nov 17 17:16:44 1999
@@ -436,14 +436,14 @@

__initfunc(static int get_model_name(struct cpuinfo_x86 *c))
{
- unsigned int n, dummy, *v;
+ unsigned int n, dummy, *v, ecx, edx;

/* Actually we must have cpuid or we could never have
* figured out that this was AMD from the vendor info :-).
*/

cpuid(0x80000000, &n, &dummy, &dummy, &dummy);
- if (n < 4)
+ if (n < 0x80000004)
return 0;
cpuid(0x80000001, &dummy, &dummy, &dummy, &(c->x86_capability));
v = (unsigned int *) c->x86_model_id;
@@ -459,6 +459,18 @@
(boot_cpu_data.x86_mask >= 8)))
c->x86_capability |= X86_FEATURE_MTRR;

+ if (n >= 0x80000005){
+ cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
+ printk("CPU: L1 I Cache: %dK L1 D Cache: %dK\n",
+ ecx>>24, edx>>24);
+ c->x86_cache_size=(ecx>>24)+(edx>>24);
+ }
+ if (n >= 0x80000006){
+ cpuid(0x80000006, &dummy, &dummy, &ecx, &edx);
+ printk("CPU: L2 Cache: %dK\n", ecx>>16);
+ c->x86_cache_size = ecx>>16;
+ }
+
return 1;
}

@@ -529,14 +541,6 @@
break;
case 6: /* An Athlon. We can trust the BIOS probably */
{
-
- u32 ecx, edx, dummy;
- cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
- printk("L1 I Cache: %dK L1 D Cache: %dK\n",
- ecx>>24, edx>>24);
- cpuid(0x80000006, &dummy, &dummy, &ecx, &edx);
- printk("L2 Cache: %dK\n", ecx>>16);
- c->x86_cache_size = ecx>>16;
break;
}
--- linux-2.3.28-clean/arch/i386/kernel/setup.c Tue Nov 9 08:10:43 1999
+++ linux-2.3.28/arch/i386/kernel/setup.c Wed Nov 17 17:12:38 1999
@@ -759,14 +759,14 @@

static int __init get_model_name(struct cpuinfo_x86 *c)
{
- unsigned int n, dummy, *v;
+ unsigned int n, dummy, *v, ecx, edx;

/* Actually we must have cpuid or we could never have
* figured out that this was AMD from the vendor info :-).
*/

cpuid(0x80000000, &n, &dummy, &dummy, &dummy);
- if (n < 4)
+ if (n < 0x80000004)
return 0;
cpuid(0x80000001, &dummy, &dummy, &dummy, &(c->x86_capability));
v = (unsigned int *) c->x86_model_id;
@@ -782,6 +782,17 @@
(boot_cpu_data.x86_mask >= 8)))
c->x86_capability |= X86_FEATURE_MTRR;

+ if (n >= 0x80000005){
+ cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
+ printk("CPU: L1 I Cache: %dK L1 D Cache: %dK\n",
+ ecx>>24, edx>>24);
+ c->x86_cache_size=(ecx>>24)+(edx>>24);
+ }
+ if (n >= 0x80000006){
+ cpuid(0x80000006, &dummy, &dummy, &ecx, &edx);
+ printk("CPU: L2 Cache: %dK\n", ecx>>16);
+ c->x86_cache_size = ecx>>16;
+ }
return 1;
}

@@ -852,14 +863,6 @@
break;
case 6: /* An Athlon. We can trust the BIOS probably */
{
-
- u32 ecx, edx, dummy;
- cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
- printk("L1 I Cache: %dK L1 D Cache: %dK\n",
- ecx>>24, edx>>24);
- cpuid(0x80000006, &dummy, &dummy, &ecx, &edx);
- printk("L2 Cache: %dK\n", ecx>>16);
- c->x86_cache_size = ecx>>16;
break;
}
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