Messages in this thread | | | Date | Wed, 9 Jul 1997 10:36:01 -0400 (EDT) | From | "Jeremy A. Gilbert" <> | Subject | Re: mmx support with smp |
| |
On Wed, 9 Jul 1997, Ricky Beam wrote:
> But isn't there some other things going on insode the CPU re: FPU/MMX use? > If you context switch a task off a processor the is using MMX, then load > any other process expecting FPU setup... > > As I remember, there is a price (a heavy one) for switching back and forth > between MMX and FPU usage. The kernel may not be able to tell what mode > the application has put the CPU in. We shall see, I'm sure.
I'm really not sure. I'm not a x86 hacker by any means. But it makes sense to me that if you are going to add new registers to a chip and you don't want to break anything, you better do your best to make existing context switching routines continue to work with the new registers. In this case, it would appear that Intel was recognizing this rubric when they overylayed the registers for the FPU/MMX. If there was a status flag that switchs between MMX and FPU mode (and I am by no means sure that there is), it probably is embedded in some other CPU state identifier is preservered. (An extra bit in a status register somewhere, maybe.)
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+ Jeremy Gilbert grath@gryphon.ccs.brandeis.edu + Webmaster & UNIX Systems Support grath@mail.cs.brandeis.edu + Department of Computer Science + Brandeis University http://gryphon.ccs.brandeis.edu/~grath + -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
| |