Messages in this thread | | | Date | Wed, 9 Jul 1997 22:06:14 +0200 (METDST) | From | Gabriel Paubert <> | Subject | Re: mmx support with smp |
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On Wed, 9 Jul 1997, Ricky Beam wrote:
> Letting the chips fall where they may, I quote Jeremy A. Gilbert: > > > >Don, > > > > I belive that since the MMX registers are overlayed over the > >FPUs floating point registers, any OS which properly performs context > >switching for the FPU will support MMX by default. This was probably a > >neccesary design aspect for Intel, since it seems to have made a definate > >commitment towards backward compatability. (If they were gonna add more > >registers, they might as well add more general purpose ones to.) > > > >Jeremy > > > > But isn't there some other things going on insode the CPU re: FPU/MMX use? > If you context switch a task off a processor the is using MMX, then load > any other process expecting FPU setup...
Jeremy is right there. The floating point save and restore context instructions simply transfer the contents of all the FP/MMX registers and do not care whether this corresponds to an FP or MMX context since they do not operate on the data. As Intel says:
"The MMX state is aliased upon the Intel Architecture floating-point state. No new state or mode is added to support the MMX technology. The same floating-point instructions that save and restore the floating-point state also handle the MMX state (for example, during context switching)."
> As I remember, there is a price (a heavy one) for switching back and forth > between MMX and FPU usage. The kernel may not be able to tell what mode > the application has put the CPU in. We shall see, I'm sure.
There is a (high) price when you switch between FPU and MMX within a thread, but context switching costs remain the same (more expensive on SMP than UP).
Gabriel.
BTW [offtopic]: A few days ago, in a bookstore here (Granada, Spain), I found a book on Linux with a sticker on it claiming (in spanish): "Includes CD-ROM with Linux version 3.0.0". Needless to say, I didn't buy that.
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