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SubjectRe: [PATCH v2 3/8] riscv: Add PLATFORM_SUPPORTS_RISCV_ISA_SVNAPOT Kconfig option
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On 08/05/2024 02:36, Charlie Jenkins wrote:
> The existing "RISCV_ISA_SVNAPOT" option is repurposed to be used to by
> kernel code to determine if either
> PLATFORM_MAY_SUPPORT_RISCV_ISA_SVNAPOT or
> PLATFORM_SUPPORTS_RISCV_ISA_SVNAPOT has been set.
>
> PLATFORM_MAY_SUPPORT_RISCV_ISA_SVNAPOT will check if the hardware
> supports Svnapot before using it, while
> PLATFORM_SUPPORTS_RISCV_ISA_SVNAPOT will assume that the hardware
> supports Svnapot.
>
> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> ---
> arch/riscv/Kconfig | 19 -----------------
> arch/riscv/Kconfig.isa | 44 ++++++++++++++++++++++++++++++++++++++++
> arch/riscv/include/asm/pgtable.h | 3 ++-
> 3 files changed, 46 insertions(+), 20 deletions(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index c2e9eded0a7d..3c1960e8cd7c 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -484,25 +484,6 @@ config RISCV_ALTERNATIVE_EARLY
> help
> Allows early patching of the kernel for special errata
>
> -config RISCV_ISA_SVNAPOT
> - bool "Svnapot extension support for supervisor mode NAPOT pages"
> - depends on 64BIT && MMU
> - depends on RISCV_ALTERNATIVE
> - default y
> - help
> - Add support for the Svnapot ISA-extension in the kernel when it
> - is detected at boot.
> -
> - The Svnapot extension is used to mark contiguous PTEs as a range
> - of contiguous virtual-to-physical translations for a naturally
> - aligned power-of-2 (NAPOT) granularity larger than the base 4KB page
> - size. When HUGETLBFS is also selected this option unconditionally
> - allocates some memory for each NAPOT page size supported by the kernel.
> - When optimizing for low memory consumption and for platforms without
> - the Svnapot extension, it may be better to say N here.
> -
> - If you don't know what to do here, say Y.
> -
> config RISCV_ISA_SVPBMT
> bool "Svpbmt extension support for supervisor mode page-based memory types"
> depends on 64BIT && MMU
> diff --git a/arch/riscv/Kconfig.isa b/arch/riscv/Kconfig.isa
> index 0663c98b5b17..37585bcd763e 100644
> --- a/arch/riscv/Kconfig.isa
> +++ b/arch/riscv/Kconfig.isa
> @@ -124,3 +124,47 @@ config RISCV_ISA_V_PREEMPTIVE
> This config allows kernel to run SIMD without explicitly disable
> preemption. Enabling this config will result in higher memory
> consumption due to the allocation of per-task's kernel Vector context.
> +
> +config RISCV_ISA_SVNAPOT
> + bool
> +
> +choice
> + prompt "Svnapot extension support for supervisor mode NAPOT pages"
> + default PLATFORM_MAY_SUPPORT_RISCV_ISA_SVNAPOT
> + help
> + This selects the level of support for Svnapot in the Linux Kernel.
> +
> + The Svnapot extension is used to mark contiguous PTEs as a range
> + of contiguous virtual-to-physical translations for a naturally
> + aligned power-of-2 (NAPOT) granularity larger than the base 4KB page
> + size. When HUGETLBFS is also selected this option unconditionally
> + allocates some memory for each NAPOT page size supported by the kernel.
> + When optimizing for low memory consumption and for platforms without
> + the Svnapot extension, it may be better to prohibit Svnapot.
> +
> +config PROHIBIT_RISCV_ISA_SVNAPOT
> + bool "Prohibit Svnapot extension"
> + help
> + Regardless of if the platform supports Svnapot, prohibit the kernel
> + from using Svnapot.
> +
> +config PLATFORM_MAY_SUPPORT_RISCV_ISA_SVNAPOT
> + bool "Allow Svnapot extension if supported"
> + depends on 64BIT && MMU
> + depends on RISCV_ALTERNATIVE
> + select RISCV_ISA_SVNAPOT
> + help
> + Add support for the Svnapot ISA-extension in the kernel when it
> + is detected at boot.
> +
> +config PLATFORM_SUPPORTS_RISCV_ISA_SVNAPOT
> + bool "Emit Svnapot mappings when building Linux"
> + depends on 64BIT && MMU
> + depends on NONPORTABLE
> + select RISCV_ISA_SVNAPOT
> + help
> + Compile a kernel that assumes that the platform supports Svnapot.
> + This option produces a kernel that will not run on systems that do
> + not support Svnapot.
> +
> +endchoice
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 6afd6bb4882e..432be9691b78 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -289,7 +289,8 @@ static inline pte_t pud_pte(pud_t pud)
>
> static __always_inline bool has_svnapot(void)
> {
> - return riscv_has_extension_likely(RISCV_ISA_EXT_SVNAPOT);
> + return IS_ENABLED(CONFIG_PLATFORM_SUPPORTS_RISCV_ISA_SVNAPOT) ||
> + riscv_has_extension_likely(RISCV_ISA_EXT_SVNAPOT);

could you add the IS_ENABLED(*) check into riscv_has_extension_likely
and other such functions?


--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html


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