Messages in this thread | | | From | Witold Sadowski <> | Subject | [PATCH v4 0/5] Marvell HW overlay support for Cadence xSPI | Date | Wed, 8 May 2024 18:05:18 -0700 |
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This patch series is adding support for second version of Marvell HW overlay for Cadence xSPI IP block. Overlay is HW change made around orginal xSPI block. Overlay extends xSPI features, with clock configuration, interrupt masking and full-duplex, variable length SPI operations. All that functionalites allows xSPI block to operate not only with memory devices, but also with simple SPI devices, or TPM devices.
Changes: v4: Rename new Marvell registers to keep naming conventions Rename mrvl,xspi-nor to marvell,cnxx,xspi-nor Various fixed for cdns,xspi.yaml file: - Remove unnecesary parameters - Link register xferbase with marvell,cn10-xspi-nor - Move default values to .c file from device-tree Clock configuration optimization ACPI fixes: - Remove incorrect ACPI match table Added .data field to device_id, fixes for matching in ACPI and dtb case Minor style comment changes
v3: Removed all kconfig changes Added device-tree mrvl,xspi-nor tag
v2: Support for second overlay iteration
v1: -
v0: Initial support for v1 overlay
Piyush Malgujar (1): spi: cadence: Allow to read basic xSPI configuration from ACPI
Witold Sadowski (4): spi: cadence: Ensure data lines set to low during dummy-cycle period dt-bindings: spi: cadence: Add MRVL overlay bindings documentation for Cadence XSPI spi: cadence: Add Marvell xSPI IP overlay changes spi: cadence: Add MRVL overlay xfer operation support
.../devicetree/bindings/spi/cdns,xspi.yaml | 78 ++- drivers/spi/spi-cadence-xspi.c | 623 +++++++++++++++++- 2 files changed, 668 insertions(+), 33 deletions(-)
-- 2.43.0
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