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SubjectRe: [PATCH v6 01/17] dt-bindings: riscv: Add xtheadvector ISA extension description
On Sat, May 4, 2024 at 3:33 AM Charlie Jenkins <charlie@rivosinc.com> wrote:
>
> The xtheadvector ISA extension is described on the T-Head extension spec
> Github page [1] at commit 95358cb2cca9.
>
> Link: https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc [1]
>
> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Reviewed-by: Andy Chiu <andy.chiu@sifive.com>

> ---
> Documentation/devicetree/bindings/riscv/extensions.yaml | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 468c646247aa..99d2a9e8c52d 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -477,6 +477,10 @@ properties:
> latency, as ratified in commit 56ed795 ("Update
> riscv-crypto-spec-vector.adoc") of riscv-crypto.
>
> + # vendor extensions, each extension sorted alphanumerically under the
> + # vendor they belong to. Vendors are sorted alphanumerically as well.
> +
> + # Andes
> - const: xandespmu
> description:
> The Andes Technology performance monitor extension for counter overflow
> @@ -484,5 +488,11 @@ properties:
> Registers in the AX45MP datasheet.
> https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
>
> + # T-HEAD
> + - const: xtheadvector
> + description:
> + The T-HEAD specific 0.7.1 vector implementation as written in
> + https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc.
> +
> additionalProperties: true
> ...
>
> --
> 2.44.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

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