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    Subject[PATCH v6 09/17] riscv: Convert xandespmu to use the vendor extension framework
    Migrate xandespmu out of riscv_isa_ext and into a new Andes-specific
    vendor namespace.

    Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
    Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
    ---
    arch/riscv/Kconfig.vendor | 12 ++++++++++++
    arch/riscv/errata/andes/errata.c | 2 ++
    arch/riscv/include/asm/hwcap.h | 1 -
    arch/riscv/include/asm/vendor_extensions/andes.h | 19 +++++++++++++++++++
    arch/riscv/kernel/cpufeature.c | 1 -
    arch/riscv/kernel/vendor_extensions.c | 10 ++++++++++
    arch/riscv/kernel/vendor_extensions/Makefile | 1 +
    arch/riscv/kernel/vendor_extensions/andes.c | 18 ++++++++++++++++++
    drivers/perf/riscv_pmu_sbi.c | 9 ++++++---
    9 files changed, 68 insertions(+), 5 deletions(-)

    diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor
    index 85ac30496b0e..aa5a191e659e 100644
    --- a/arch/riscv/Kconfig.vendor
    +++ b/arch/riscv/Kconfig.vendor
    @@ -16,4 +16,16 @@ config RISCV_ISA_VENDOR_EXT_THEAD
    If you don't know what to do here, say Y.
    endmenu

    +menu "Andes"
    +config RISCV_ISA_VENDOR_EXT_ANDES
    + bool "Andes vendor extension support"
    + default y
    + help
    + Say N here if you want to disable all Andes vendor extension
    + support. This will cause any Andes vendor extensions that are
    + requested by hardware probing to be ignored.
    +
    + If you don't know what to do here, say Y.
    +endmenu
    +
    endmenu
    diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c
    index f2708a9494a1..a5d96a7a4682 100644
    --- a/arch/riscv/errata/andes/errata.c
    +++ b/arch/riscv/errata/andes/errata.c
    @@ -65,6 +65,8 @@ void __init_or_module andes_errata_patch_func(struct alt_entry *begin, struct al
    unsigned long archid, unsigned long impid,
    unsigned int stage)
    {
    + BUILD_BUG_ON(ERRATA_ANDES_NUMBER >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE);
    +
    if (stage == RISCV_ALTERNATIVES_BOOT)
    errata_probe_iocp(stage, archid, impid);

    diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
    index e17d0078a651..1f2d2599c655 100644
    --- a/arch/riscv/include/asm/hwcap.h
    +++ b/arch/riscv/include/asm/hwcap.h
    @@ -80,7 +80,6 @@
    #define RISCV_ISA_EXT_ZFA 71
    #define RISCV_ISA_EXT_ZTSO 72
    #define RISCV_ISA_EXT_ZACAS 73
    -#define RISCV_ISA_EXT_XANDESPMU 74

    #define RISCV_ISA_EXT_XLINUXENVCFG 127

    diff --git a/arch/riscv/include/asm/vendor_extensions/andes.h b/arch/riscv/include/asm/vendor_extensions/andes.h
    new file mode 100644
    index 000000000000..7bb2fc43438f
    --- /dev/null
    +++ b/arch/riscv/include/asm/vendor_extensions/andes.h
    @@ -0,0 +1,19 @@
    +/* SPDX-License-Identifier: GPL-2.0 */
    +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_ANDES_H
    +#define _ASM_RISCV_VENDOR_EXTENSIONS_ANDES_H
    +
    +#include <asm/vendor_extensions.h>
    +
    +#include <linux/types.h>
    +
    +#define RISCV_ISA_VENDOR_EXT_XANDESPMU 0
    +
    +/*
    + * Extension keys should be strictly less than max.
    + * It is safe to increment this when necessary.
    + */
    +#define RISCV_ISA_VENDOR_EXT_MAX_ANDES 32
    +
    +extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_andes;
    +
    +#endif
    diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
    index 2a5527020d0f..2993318b8ea2 100644
    --- a/arch/riscv/kernel/cpufeature.c
    +++ b/arch/riscv/kernel/cpufeature.c
    @@ -289,7 +289,6 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
    __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
    __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
    __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
    - __RISCV_ISA_EXT_DATA(xandespmu, RISCV_ISA_EXT_XANDESPMU),
    };

    const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
    diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vendor_extensions.c
    index 7910890c17de..e4d58938e6ce 100644
    --- a/arch/riscv/kernel/vendor_extensions.c
    +++ b/arch/riscv/kernel/vendor_extensions.c
    @@ -5,6 +5,7 @@

    #include <asm/vendorid_list.h>
    #include <asm/vendor_extensions.h>
    +#include <asm/vendor_extensions/andes.h>
    #include <asm/vendor_extensions/thead.h>

    #include <linux/array_size.h>
    @@ -14,6 +15,9 @@ struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_ext_list[] = {
    #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD
    &riscv_isa_vendor_ext_list_thead,
    #endif
    +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_ANDES
    + &riscv_isa_vendor_ext_list_andes,
    +#endif
    };

    const size_t riscv_isa_vendor_ext_list_size = ARRAY_SIZE(riscv_isa_vendor_ext_list);
    @@ -40,6 +44,12 @@ bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsig
    bmap = &riscv_isa_vendor_ext_list_thead.all_harts_isa_bitmap;
    cpu_bmap = &riscv_isa_vendor_ext_list_thead.per_hart_isa_bitmap[cpu];
    break;
    +#endif
    +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_ANDES
    + case ANDES_VENDOR_ID:
    + bmap = &riscv_isa_vendor_ext_list_andes.all_harts_isa_bitmap;
    + cpu_bmap = &riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap[cpu];
    + break;
    #endif
    default:
    return false;
    diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kernel/vendor_extensions/Makefile
    index 3383066baaab..8f1c5a4dc38f 100644
    --- a/arch/riscv/kernel/vendor_extensions/Makefile
    +++ b/arch/riscv/kernel/vendor_extensions/Makefile
    @@ -1,3 +1,4 @@
    # SPDX-License-Identifier: GPL-2.0-only

    obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead.o
    +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) += andes.o
    diff --git a/arch/riscv/kernel/vendor_extensions/andes.c b/arch/riscv/kernel/vendor_extensions/andes.c
    new file mode 100644
    index 000000000000..ec688c88456a
    --- /dev/null
    +++ b/arch/riscv/kernel/vendor_extensions/andes.c
    @@ -0,0 +1,18 @@
    +// SPDX-License-Identifier: GPL-2.0-only
    +
    +#include <asm/cpufeature.h>
    +#include <asm/vendor_extensions.h>
    +#include <asm/vendor_extensions/andes.h>
    +
    +#include <linux/array_size.h>
    +#include <linux/types.h>
    +
    +/* All Andes vendor extensions supported in Linux */
    +const struct riscv_isa_ext_data riscv_isa_vendor_ext_andes[] = {
    + __RISCV_ISA_EXT_DATA(xandespmu, RISCV_ISA_VENDOR_EXT_XANDESPMU),
    +};
    +
    +struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_andes = {
    + .ext_data_count = ARRAY_SIZE(riscv_isa_vendor_ext_andes),
    + .ext_data = riscv_isa_vendor_ext_andes,
    +};
    diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
    index 8cbe6e5f9c39..d39b01372fa5 100644
    --- a/drivers/perf/riscv_pmu_sbi.c
    +++ b/drivers/perf/riscv_pmu_sbi.c
    @@ -24,6 +24,8 @@
    #include <asm/errata_list.h>
    #include <asm/sbi.h>
    #include <asm/cpufeature.h>
    +#include <asm/vendorid_list.h>
    +#include <asm/vendor_extensions/andes.h>

    #define ALT_SBI_PMU_OVERFLOW(__ovl) \
    asm volatile(ALTERNATIVE_2( \
    @@ -32,7 +34,7 @@ asm volatile(ALTERNATIVE_2( \
    THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \
    CONFIG_ERRATA_THEAD_PMU, \
    "csrr %0, " __stringify(ANDES_CSR_SCOUNTEROF), \
    - 0, RISCV_ISA_EXT_XANDESPMU, \
    + ANDES_VENDOR_ID, RISCV_ISA_VENDOR_EXT_XANDESPMU, \
    CONFIG_ANDES_CUSTOM_PMU) \
    : "=r" (__ovl) : \
    : "memory")
    @@ -41,7 +43,7 @@ asm volatile(ALTERNATIVE_2( \
    asm volatile(ALTERNATIVE( \
    "csrc " __stringify(CSR_IP) ", %0\n\t", \
    "csrc " __stringify(ANDES_CSR_SLIP) ", %0\n\t", \
    - 0, RISCV_ISA_EXT_XANDESPMU, \
    + ANDES_VENDOR_ID, RISCV_ISA_VENDOR_EXT_XANDESPMU, \
    CONFIG_ANDES_CUSTOM_PMU) \
    : : "r"(__irq_mask) \
    : "memory")
    @@ -837,7 +839,8 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
    riscv_cached_mimpid(0) == 0) {
    riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU;
    riscv_pmu_use_irq = true;
    - } else if (riscv_isa_extension_available(NULL, XANDESPMU) &&
    + } else if (riscv_has_vendor_extension_unlikely(ANDES_VENDOR_ID,
    + RISCV_ISA_VENDOR_EXT_XANDESPMU) &&
    IS_ENABLED(CONFIG_ANDES_CUSTOM_PMU)) {
    riscv_pmu_irq_num = ANDES_SLI_CAUSE_BASE + ANDES_RV_IRQ_PMOVI;
    riscv_pmu_use_irq = true;
    --
    2.44.0


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