Messages in this thread | | | Date | Sun, 14 Apr 2024 08:53:32 -0700 | Subject | Re: [PATCH 5/6] mmc: sdhci-brcmstb: Add BCM2712 support | From | Florian Fainelli <> |
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On 4/13/2024 3:14 PM, Andrea della Porta wrote: > Broadcom BCM2712 SoC has an SDHCI card controller using the SDIO CFG > register block present on other STB chips. Add support for BCM2712 > SD capabilities of this chipset. > The silicon is SD Express capable but this driver port does not currently > include that feature yet. > Based on downstream driver by raspberry foundation maintained kernel. > > Signed-off-by: Andrea della Porta <andrea.porta@suse.com> > --- > drivers/mmc/host/sdhci-brcmstb.c | 130 +++++++++++++++++++++++++++++++ > 1 file changed, 130 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c > index 9053526fa212..907a4947abe5 100644 > --- a/drivers/mmc/host/sdhci-brcmstb.c > +++ b/drivers/mmc/host/sdhci-brcmstb.c > @@ -12,6 +12,8 @@ > #include <linux/of.h> > #include <linux/bitops.h> > #include <linux/delay.h> > +#include <linux/pinctrl/consumer.h> > +#include <linux/regulator/consumer.h> > > #include "sdhci-cqhci.h" > #include "sdhci-pltfm.h" > @@ -30,15 +32,31 @@ > > #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 > > +#define SDIO_CFG_CTRL 0x0 > +#define SDIO_CFG_CTRL_SDCD_N_TEST_EN BIT(31) > +#define SDIO_CFG_CTRL_SDCD_N_TEST_LEV BIT(30) > + > +#define SDIO_CFG_SD_PIN_SEL 0x44 > +#define SDIO_CFG_SD_PIN_SEL_MASK 0x3 > +#define SDIO_CFG_SD_PIN_SEL_SD BIT(1) > +#define SDIO_CFG_SD_PIN_SEL_MMC BIT(0) > + > +#define SDIO_CFG_MAX_50MHZ_MODE 0x1ac > +#define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31) > +#define SDIO_CFG_MAX_50MHZ_MODE_ENABLE BIT(0) > + > struct sdhci_brcmstb_priv { > void __iomem *cfg_regs; > unsigned int flags; > struct clk *base_clk; > u32 base_freq_hz; > + struct pinctrl *pinctrl; > + struct pinctrl_state *pins_default; > }; > > struct brcmstb_match_priv { > void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); > + void (*cfginit)(struct sdhci_host *host); > struct sdhci_ops *ops; > const unsigned int flags; > }; > @@ -124,6 +142,42 @@ static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios) > writel(reg, host->ioaddr + SDHCI_VENDOR); > } > > +static void sdhci_bcm2712_set_clock(struct sdhci_host *host, unsigned int clock) > +{ > + u16 clk; > + u32 reg; > + bool is_emmc_rate = false; > + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > + struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host);
Reverse christmas tree declaration please, longest lines first and shortest lines next.
> + > + host->mmc->actual_clock = 0; > + > + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); > + > + switch (host->mmc->ios.timing) { > + case MMC_TIMING_MMC_HS400: > + case MMC_TIMING_MMC_HS200: > + case MMC_TIMING_MMC_DDR52: > + case MMC_TIMING_MMC_HS: > + is_emmc_rate = true; > + break;
Both lines are mis-aligned and requiren an additional tab.
> + } > + > + reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_SD_PIN_SEL); > + reg &= ~SDIO_CFG_SD_PIN_SEL_MASK; > + if (is_emmc_rate) > + reg |= SDIO_CFG_SD_PIN_SEL_MMC; > + else > + reg |= SDIO_CFG_SD_PIN_SEL_SD; > + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_SD_PIN_SEL); > + > + if (clock == 0) > + return; > + > + clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); > + sdhci_enable_clk(host, clk); > +} > + > static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock) > { > u16 clk; > @@ -139,6 +193,17 @@ static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock) > sdhci_enable_clk(host, clk); > } > > +static void sdhci_brcmstb_set_power(struct sdhci_host *host, unsigned char mode, > + unsigned short vdd) > +{ > + if (!IS_ERR(host->mmc->supply.vmmc)) { > + struct mmc_host *mmc = host->mmc; > + > + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); > + } > + sdhci_set_power_noreg(host, mode, vdd); > +} > + > static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host, > unsigned int timing) > { > @@ -168,6 +233,36 @@ static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host, > sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); > } > > +static void sdhci_brcmstb_cfginit_2712(struct sdhci_host *host) > +{ > + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > + struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host); > + u32 uhs_mask = (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104); > + u32 hsemmc_mask = (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS200_1_2V_SDR | > + MMC_CAP2_HS400_1_8V | MMC_CAP2_HS400_1_2V); > + u32 reg; > + > + /* > + * If we support a speed that requires tuning, > + * then select the delay line PHY as the clock source. > + */ > + if ((host->mmc->caps & uhs_mask) || (host->mmc->caps2 & hsemmc_mask)) { > + reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE); > + reg &= ~SDIO_CFG_MAX_50MHZ_MODE_ENABLE; > + reg |= SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE; > + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE); > + } > + > + if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || > + (host->mmc->caps & MMC_CAP_NEEDS_POLL)) { > + /* Force presence */ > + reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_CTRL); > + reg &= ~SDIO_CFG_CTRL_SDCD_N_TEST_LEV; > + reg |= SDIO_CFG_CTRL_SDCD_N_TEST_EN; > + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_CTRL); > + } > +} > + > static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc) > { > sdhci_dumpregs(mmc_priv(mmc)); > @@ -200,6 +295,14 @@ static struct sdhci_ops sdhci_brcmstb_ops = { > .set_uhs_signaling = sdhci_set_uhs_signaling, > }; > > +static struct sdhci_ops sdhci_brcmstb_ops_2712 = { > + .set_clock = sdhci_bcm2712_set_clock, > + .set_power = sdhci_brcmstb_set_power, > + .set_bus_width = sdhci_set_bus_width, > + .reset = sdhci_reset, > + .set_uhs_signaling = sdhci_set_uhs_signaling, > +}; > + > static struct sdhci_ops sdhci_brcmstb_ops_7216 = { > .set_clock = sdhci_brcmstb_set_clock, > .set_bus_width = sdhci_set_bus_width, > @@ -237,7 +340,13 @@ static struct brcmstb_match_priv match_priv_74165b0 = { > .ops = &sdhci_brcmstb_ops_74165b0, > }; > > +static const struct brcmstb_match_priv match_priv_2712 = { > + .cfginit = sdhci_brcmstb_cfginit_2712, > + .ops = &sdhci_brcmstb_ops_2712, > +}; > + > static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] = { > + { .compatible = "brcm,bcm2712-sdhci", .data = &match_priv_2712 }, > { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 }, > { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 }, > { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 }, > @@ -314,11 +423,16 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) > struct sdhci_brcmstb_priv *priv; > u32 actual_clock_mhz; > struct sdhci_host *host; > + bool no_pinctrl = false; > struct clk *clk; > struct clk *base_clk = NULL; > int res; > > match = of_match_node(sdhci_brcm_of_match, pdev->dev.of_node); > + if (!match) { > + dev_err(&pdev->dev, "fail to get matching of_match struct\n"); > + return -EINVAL; > + } > match_priv = match->data; > > dev_dbg(&pdev->dev, "Probe found match for %s\n", match->compatible); > @@ -354,6 +468,19 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) > if (res) > goto err; > > + priv->pinctrl = devm_pinctrl_get(&pdev->dev); > + if (IS_ERR(priv->pinctrl)) { > + no_pinctrl = true;
One too many tabs here.
> + } > + priv->pins_default = pinctrl_lookup_state(priv->pinctrl, "default"); > + if (IS_ERR(priv->pins_default)) { > + dev_dbg(&pdev->dev, "No pinctrl default state\n"); > + no_pinctrl = true;
One too many tabs here.
Please just run checkpatch on your patches, thanks. -- Florian [unhandled content-type:application/pkcs7-signature]
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