Messages in this thread | | | From | Charlie Jenkins <> | Subject | [PATCH v2 0/2] riscv: Extension parsing fixes | Date | Fri, 26 Apr 2024 14:58:53 -0700 |
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This series contains two minor fixes for the extension parsing in cpufeature.c.
Some T-Head boards without vector 1.0 support report "v" in the isa string in their DT which will cause the kernel to run vector code. The code to blacklist "v" from these boards was doing so by using riscv_cached_mvendorid() which has not been populated at the time of extension parsing. This fix instead greedily reads the mvendorid CSR of the boot hart to determine if the cpu is from T-Head.
The other fix is for an incorrect indexing bug. riscv extensions sometimes imply other extensions. When adding these "subset" extensions to the hardware capabilities array, they need to be checked if they are valid. The current code only checks if the extension that is including other extensions is valid and not the subset extensions.
These patches were previously included in: https://lore.kernel.org/lkml/20240420-dev-charlie-support_thead_vector_6_9-v3-0-67cff4271d1d@rivosinc.com/
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> --- Changes in v2: - Move comment about assuming all harts to have the same vendorid/archid to apply specifically to the code that expects that (Drew) - Link to v1: https://lore.kernel.org/r/20240424-cpufeature_fixes-v1-0-585e73d2226b@rivosinc.com
--- Charlie Jenkins (2): riscv: cpufeature: Fix thead vector hwcap removal riscv: cpufeature: Fix extension subset checking
arch/riscv/include/asm/sbi.h | 2 ++ arch/riscv/kernel/cpu.c | 40 ++++++++++++++++++++++++++++++++++++---- arch/riscv/kernel/cpufeature.c | 13 ++++++++++--- 3 files changed, 48 insertions(+), 7 deletions(-) --- base-commit: ed30a4a51bb196781c8058073ea720133a65596f change-id: 20240424-cpufeature_fixes-91bec4d793e7 -- - Charlie
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