lkml.org 
[lkml]   [2024]   [Mar]   [25]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
Subject[PATCH v3 RESEND 0/2] riscv: enable lockless lockref implementation
Date
This series selects ARCH_USE_CMPXCHG_LOCKREF to enable the
cmpxchg-based lockless lockref implementation for riscv. Then,
implement arch_cmpxchg64_{relaxed|acquire|release}.

After patch1:
Using Linus' test case[1] on TH1520 platform, I see a 11.2% improvement.
On JH7110 platform, I see 12.0% improvement.

After patch2:
on both TH1520 and JH7110 platforms, I didn't see obvious
performance improvement with Linus' test case [1]. IMHO, this may
be related with the fence and lr.d/sc.d hw implementations. In theory,
lr/sc without fence could give performance improvement over lr/sc plus
fence, so add the code here to leave performance improvement room on
newer HW platforms.

Link: http://marc.info/?l=linux-fsdevel&m=137782380714721&w=4 [1]

Since v2:
- rebase on v6.8-rc1
- collect Reviewed-by tag

Since v1:
- only select ARCH_USE_CMPXCHG_LOCKREF if 64BIT

Jisheng Zhang (2):
riscv: select ARCH_USE_CMPXCHG_LOCKREF
riscv: cmpxchg: implement arch_cmpxchg64_{relaxed|acquire|release}

arch/riscv/Kconfig | 1 +
arch/riscv/include/asm/cmpxchg.h | 18 ++++++++++++++++++
2 files changed, 19 insertions(+)

--
2.43.0


\
 
 \ /
  Last update: 2024-05-27 16:07    [W:0.065 / U:0.264 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site