Messages in this thread | | | Date | Tue, 9 Apr 2024 14:33:18 +0100 | Subject | Re: [PATCH] perf vendor events arm64: AmpereOne/AmpereOneX: Mark L1D_CACHE_INVAL impacted by errata | From | James Clark <> |
| |
On 08/04/2024 22:40, Ilkka Koskinen wrote: > L1D_CACHE_INVAL overcounts in certain situations. See AC03_CPU_41 and > AC04_CPU_1 for more details. Mark the event impacted by the errata. > > Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> > --- > tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json | 4 +++- > tools/perf/pmu-events/arch/arm64/ampere/ampereonex/cache.json | 4 +++- > 2 files changed, 6 insertions(+), 2 deletions(-) > > diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json > index 7a2b7b200f14..ac75f12e27bf 100644 > --- a/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json > +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json > @@ -9,7 +9,9 @@ > "ArchStdEvent": "L1D_CACHE_REFILL_RD" > }, > { > - "ArchStdEvent": "L1D_CACHE_INVAL" > + "ArchStdEvent": "L1D_CACHE_INVAL", > + "Errata": "Errata AC03_CPU_41", > + "BriefDescription": "L1D cache invalidate. Impacted by errata -" > }, > { > "ArchStdEvent": "L1D_TLB_REFILL_RD" > diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/cache.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/cache.json > index c50d8e930b05..f4bfe7083a6b 100644 > --- a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/cache.json > +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/cache.json > @@ -9,7 +9,9 @@ > "ArchStdEvent": "L1D_CACHE_REFILL_RD" > }, > { > - "ArchStdEvent": "L1D_CACHE_INVAL" > + "ArchStdEvent": "L1D_CACHE_INVAL", > + "Errata": "Errata AC04_CPU_1", > + "BriefDescription": "L1D cache invalidate. Impacted by errata -" > }, > { > "ArchStdEvent": "L1D_TLB_REFILL_RD"
Reviewed-by: James Clark <james.clark@arm.com>
| |