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    Subject[PATCH v5 1/1] dt-bindings: net: dwmac: Document STM32 property st,ext-phyclk
    Date
    The Linux kernel dwmac-stm32 driver currently supports three DT
    properties used to configure whether PHY clock are generated by
    the MAC or supplied to the MAC from the PHY.

    Originally there were two properties, st,eth-clk-sel and
    st,eth-ref-clk-sel, each used to configure MAC clocking in
    different bus mode and for different MAC clock frequency.
    Since it is possible to determine the MAC 'eth-ck' clock
    frequency from the clock subsystem and PHY bus mode from
    the 'phy-mode' property, two disparate DT properties are
    no longer required to configure MAC clocking.

    Linux kernel commit 1bb694e20839 ("net: ethernet: stmmac: simplify phy modes management for stm32")
    introduced a third, unified, property st,ext-phyclk. This property
    covers both use cases of st,eth-clk-sel and st,eth-ref-clk-sel DT
    properties, as well as a new use case for 25 MHz clock generated
    by the MAC.

    The third property st,ext-phyclk is so far undocumented,
    document it.

    Below table summarizes the clock requirement and clock sources for
    supported PHY interface modes.
    __________________________________________________________________________
    |PHY_MODE | Normal | PHY wo crystal| PHY wo crystal |No 125Mhz from PHY|
    | | | 25MHz | 50MHz | |

    ---------------------------------------------------------------------------
    | MII | - | eth-ck | n/a | n/a |
    | | | st,ext-phyclk | | |

    ---------------------------------------------------------------------------
    | GMII | - | eth-ck | n/a | n/a |
    | | | st,ext-phyclk | | |

    ---------------------------------------------------------------------------
    | RGMII | - | eth-ck | n/a | eth-ck |
    | | | st,ext-phyclk | | st,eth-clk-sel or|
    | | | | | st,ext-phyclk |

    ---------------------------------------------------------------------------
    | RMII | - | eth-ck | eth-ck | n/a |
    | | | st,ext-phyclk | st,eth-ref-clk-sel | |
    | | | | or st,ext-phyclk | |

    ---------------------------------------------------------------------------

    Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
    Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
    ---
    Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 7 +++++++
    1 file changed, 7 insertions(+)

    diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
    index fc8c96b08d7dc..b35eae80ed6ac 100644
    --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
    +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
    @@ -82,6 +82,13 @@ properties:
    Should be phandle/offset pair. The phandle to the syscon node which
    encompases the glue register, and the offset of the control register

    +st,ext-phyclk:
    + description:
    + set this property in RMII mode when you have PHY without crystal 50MHz and want to
    + select RCC clock instead of ETH_REF_CLK. OR in RGMII mode when you want to select
    + RCC clock instead of ETH_CLK125.
    + type: boolean
    +
    st,eth-clk-sel:
    description:
    set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.
    --
    2.25.1

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