Messages in this thread Patch in this message | ![/](/images/icornerl.gif) | | From | Varadarajan Narayanan <> | Subject | [PATCH v4 1/3] dt-bindings: interconnect: Add Qualcomm IPQ9574 support | Date | Wed, 27 Mar 2024 13:48:48 +0530 |
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Add interconnect-cells to clock provider so that it can be used as icc provider.
Add master/slave ids for Qualcomm IPQ9574 Network-On-Chip interfaces. This will be used by the gcc-ipq9574 driver that will for providing interconnect services using the icc-clk framework.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> --- v3: Squash Documentation/ and include/ changes into same patch
qcom,ipq9574.h Move 'first id' to clock driver
--- .../bindings/clock/qcom,ipq9574-gcc.yaml | 3 + .../dt-bindings/interconnect/qcom,ipq9574.h | 59 +++++++++++++++++++ 2 files changed, 62 insertions(+) create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml index 944a0ea79cd6..824781cbdf34 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml @@ -33,6 +33,9 @@ properties: - description: PCIE30 PHY3 pipe clock source - description: USB3 PHY pipe clock source + '#interconnect-cells': + const: 1 + required: - compatible - clocks diff --git a/include/dt-bindings/interconnect/qcom,ipq9574.h b/include/dt-bindings/interconnect/qcom,ipq9574.h new file mode 100644 index 000000000000..9c95fbd5dc46 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,ipq9574.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +#ifndef INTERCONNECT_QCOM_IPQ9574_H +#define INTERCONNECT_QCOM_IPQ9574_H + +#define MASTER_ANOC_PCIE0_1 0 +#define SLAVE_ANOC_PCIE0_1 1 +#define MASTER_SNOC_PCIE0_1 2 +#define SLAVE_SNOC_PCIE0_1 3 +#define MASTER_ANOC_PCIE1_1 4 +#define SLAVE_ANOC_PCIE1_1 5 +#define MASTER_SNOC_PCIE1_1 6 +#define SLAVE_SNOC_PCIE1_1 7 +#define MASTER_ANOC_PCIE2_2 8 +#define SLAVE_ANOC_PCIE2_2 9 +#define MASTER_SNOC_PCIE2_2 10 +#define SLAVE_SNOC_PCIE2_2 11 +#define MASTER_ANOC_PCIE3_2 12 +#define SLAVE_ANOC_PCIE3_2 13 +#define MASTER_SNOC_PCIE3_2 14 +#define SLAVE_SNOC_PCIE3_2 15 +#define MASTER_USB 16 +#define SLAVE_USB 17 +#define MASTER_USB_AXI 18 +#define SLAVE_USB_AXI 19 +#define MASTER_NSSNOC_NSSCC 20 +#define SLAVE_NSSNOC_NSSCC 21 +#define MASTER_NSSNOC_SNOC 22 +#define SLAVE_NSSNOC_SNOC 23 +#define MASTER_NSSNOC_SNOC_1 24 +#define SLAVE_NSSNOC_SNOC_1 25 +#define MASTER_NSSNOC_PCNOC_1 26 +#define SLAVE_NSSNOC_PCNOC_1 27 +#define MASTER_NSSNOC_QOSGEN_REF 28 +#define SLAVE_NSSNOC_QOSGEN_REF 29 +#define MASTER_NSSNOC_TIMEOUT_REF 30 +#define SLAVE_NSSNOC_TIMEOUT_REF 31 +#define MASTER_NSSNOC_XO_DCD 32 +#define SLAVE_NSSNOC_XO_DCD 33 +#define MASTER_NSSNOC_ATB 34 +#define SLAVE_NSSNOC_ATB 35 +#define MASTER_MEM_NOC_NSSNOC 36 +#define SLAVE_MEM_NOC_NSSNOC 37 +#define MASTER_NSSNOC_MEMNOC 38 +#define SLAVE_NSSNOC_MEMNOC 39 +#define MASTER_NSSNOC_MEM_NOC_1 40 +#define SLAVE_NSSNOC_MEM_NOC_1 41 + +#define MASTER_NSS_CC_NSSNOC_PPE 0 +#define SLAVE_NSS_CC_NSSNOC_PPE 1 +#define MASTER_NSS_CC_NSSNOC_PPE_CFG 2 +#define SLAVE_NSS_CC_NSSNOC_PPE_CFG 3 +#define MASTER_NSS_CC_NSSNOC_NSS_CSR 4 +#define SLAVE_NSS_CC_NSSNOC_NSS_CSR 5 +#define MASTER_NSS_CC_NSSNOC_IMEM_QSB 6 +#define SLAVE_NSS_CC_NSSNOC_IMEM_QSB 7 +#define MASTER_NSS_CC_NSSNOC_IMEM_AHB 8 +#define SLAVE_NSS_CC_NSSNOC_IMEM_AHB 9 + +#endif /* INTERCONNECT_QCOM_IPQ9574_H */ -- 2.34.1
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