Messages in this thread | | | Date | Wed, 27 Mar 2024 15:27:31 +0800 | Subject | Re: [PATCH bpf-next v3 1/2] bpf,riscv: Implement PROBE_MEM32 pseudo instructions | From | Pu Lehui <> |
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On 2024/3/27 6:49, Puranjay Mohan wrote: > Add support for [LDX | STX | ST], PROBE_MEM32, [B | H | W | DW] [SNIP] > if (WARN_ON_ONCE(ctx->nexentries >= ctx->prog->aux->num_exentries)) > @@ -1539,6 +1547,11 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, > case BPF_LDX | BPF_PROBE_MEMSX | BPF_B: > case BPF_LDX | BPF_PROBE_MEMSX | BPF_H: > case BPF_LDX | BPF_PROBE_MEMSX | BPF_W: > + /* LDX | PROBE_MEM32: dst = *(unsigned size *)(src + S7 + off)*/
still some nits. please align, change S7 here to reg_arena.
> + case BPF_LDX | BPF_PROBE_MEM32 | BPF_B: > + case BPF_LDX | BPF_PROBE_MEM32 | BPF_H: > + case BPF_LDX | BPF_PROBE_MEM32 | BPF_W: > + case BPF_LDX | BPF_PROBE_MEM32 | BPF_DW: [SNIP] > + > + switch (BPF_SIZE(code)) { > + case BPF_B: > + if (is_12b_int(off)) { > + insns_start = ctx->ninsns; > + emit(rv_sb(rd, off, RV_REG_T1), ctx); > + insn_len = ctx->ninsns - insns_start; > + break; > + } > + > + emit_imm(RV_REG_T2, off, ctx); > + emit_add(RV_REG_T2, RV_REG_T2, rd, ctx); > + insns_start = ctx->ninsns; > + emit(rv_sb(RV_REG_T2, 0, RV_REG_T1), ctx); > + insn_len = ctx->ninsns - insns_start; > + redundant blank. > + break; > + ditto.
Others, looks good to me.
Reviewed-by: Pu Lehui <pulehui@huawei.com> Tested-by: Pu Lehui <pulehui@huawei.com>
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