Messages in this thread | | | Date | Wed, 27 Mar 2024 18:45:04 +0100 | From | Sebastian Reichel <> | Subject | Re: [PATCH v2 2/2] arm64: dts: rockchip: Add VEPU121 to rk3588 |
| |
Hi,
On Wed, Mar 27, 2024 at 02:41:12PM +0100, Emmanuel Gil Peyrot wrote: > The TRM (version 1.0 page 385) lists five VEPU121 cores, but only four > interrupts are listed (on page 24), so I’ve only enabled four of them > for now. > > Signed-off-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr> > ---
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-- Sebastian
> arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 80 +++++++++++++++++++++++ > 1 file changed, 80 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi > index 87b83c87bd55..510ed3db9d01 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi > @@ -2488,6 +2488,86 @@ gpio4: gpio@fec50000 { > }; > }; > > + jpeg_enc0: video-codec@fdba0000 { > + compatible = "rockchip,rk3588-vepu121", "rockchip,rk3568-vepu"; > + reg = <0x0 0xfdba0000 0x0 0x800>; > + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; > + clock-names = "aclk", "hclk"; > + iommus = <&jpeg_enc0_mmu>; > + power-domains = <&power RK3588_PD_VDPU>; > + }; > + > + jpeg_enc0_mmu: iommu@fdba0800 { > + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; > + reg = <0x0 0xfdba0800 0x0 0x40>; > + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; > + clock-names = "aclk", "iface"; > + power-domains = <&power RK3588_PD_VDPU>; > + #iommu-cells = <0>; > + }; > + > + jpeg_enc1: video-codec@fdba4000 { > + compatible = "rockchip,rk3588-vepu121", "rockchip,rk3568-vepu"; > + reg = <0x0 0xfdba4000 0x0 0x800>; > + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; > + clock-names = "aclk", "hclk"; > + iommus = <&jpeg_enc1_mmu>; > + power-domains = <&power RK3588_PD_VDPU>; > + }; > + > + jpeg_enc1_mmu: iommu@fdba4800 { > + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; > + reg = <0x0 0xfdba4800 0x0 0x40>; > + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; > + clock-names = "aclk", "iface"; > + power-domains = <&power RK3588_PD_VDPU>; > + #iommu-cells = <0>; > + }; > + > + jpeg_enc2: video-codec@fdba8000 { > + compatible = "rockchip,rk3588-vepu121", "rockchip,rk3568-vepu"; > + reg = <0x0 0xfdba8000 0x0 0x800>; > + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; > + clock-names = "aclk", "hclk"; > + iommus = <&jpeg_enc2_mmu>; > + power-domains = <&power RK3588_PD_VDPU>; > + }; > + > + jpeg_enc2_mmu: iommu@fdba8800 { > + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; > + reg = <0x0 0xfdba8800 0x0 0x40>; > + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; > + clock-names = "aclk", "iface"; > + power-domains = <&power RK3588_PD_VDPU>; > + #iommu-cells = <0>; > + }; > + > + jpeg_enc3: video-codec@fdbac000 { > + compatible = "rockchip,rk3588-vepu121", "rockchip,rk3568-vepu"; > + reg = <0x0 0xfdbac000 0x0 0x800>; > + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; > + clock-names = "aclk", "hclk"; > + iommus = <&jpeg_enc3_mmu>; > + power-domains = <&power RK3588_PD_VDPU>; > + }; > + > + jpeg_enc3_mmu: iommu@fdbac800 { > + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; > + reg = <0x0 0xfdbac800 0x0 0x40>; > + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; > + clock-names = "aclk", "iface"; > + power-domains = <&power RK3588_PD_VDPU>; > + #iommu-cells = <0>; > + }; > + > av1d: video-codec@fdc70000 { > compatible = "rockchip,rk3588-av1-vpu"; > reg = <0x0 0xfdc70000 0x0 0x800>; > -- > 2.44.0 > [unhandled content-type:application/pgp-signature] | |