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    Subject[PATCH v2 07/21] arm64: dts: qcom: sm8650: Add PCIe bridge node
    On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
    for each controller instance. Hence, add a node to represent the bridge.

    Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
    Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
    ---
    arch/arm64/boot/dts/qcom/sm8650.dtsi | 20 ++++++++++++++++++++
    1 file changed, 20 insertions(+)

    diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
    index ba72d8f38420..06d2b6432ab1 100644
    --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
    +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
    @@ -2294,6 +2294,16 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
    dma-coherent;

    status = "disabled";
    +
    + pcie@0 {
    + device_type = "pci";
    + reg = <0x0 0x0 0x0 0x0 0x0>;
    + bus-range = <0x01 0xff>;
    +
    + #address-cells = <3>;
    + #size-cells = <2>;
    + ranges;
    + };
    };

    pcie0_phy: phy@1c06000 {
    @@ -2422,6 +2432,16 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
    <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>;

    status = "disabled";
    +
    + pcie@0 {
    + device_type = "pci";
    + reg = <0x0 0x0 0x0 0x0 0x0>;
    + bus-range = <0x01 0xff>;
    +
    + #address-cells = <3>;
    + #size-cells = <2>;
    + ranges;
    + };
    };

    pcie1_phy: phy@1c0e000 {
    --
    2.25.1


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