Messages in this thread | | | Date | Thu, 8 Feb 2024 15:58:10 +0530 | Subject | Re: [RFC 1/7] dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings | From | Sibi Sankar <> |
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On 1/30/24 22:42, Rob Herring wrote: > On Wed, Jan 17, 2024 at 11:04:52PM +0530, Sibi Sankar wrote: >> Add devicetree binding for CPUSS Control Processor (CPUCP) mailbox >> controller.
Hey Rob,
Thanks for taking time to review the series.
>> >> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> >> --- >> .../bindings/mailbox/qcom,cpucp-mbox.yaml | 51 +++++++++++++++++++ >> 1 file changed, 51 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml >> >> diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml >> new file mode 100644 >> index 000000000000..2617e5555acb >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml >> @@ -0,0 +1,51 @@ >> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller >> + >> +maintainers: >> + - Sibi Sankar <quic_sibis@qti.qualcomm.com> >> + >> +description: >> + The CPUSS Control Processor (CPUCP) mailbox controller enables communication >> + between AP and CPUCP by acting as a doorbell between them. >> + >> +properties: >> + compatible: >> + items: >> + - enum: >> + - qcom,x1e80100-cpucp-mbox >> + - const: qcom,cpucp-mbox > > A generic fallback implies multiple devices use the same unchanged > block. That seems doubtful given you have not defined any others and > given Konrad's comments.
This mbox is expected to be used as is on a number of future SoCs, that's the only reason I added the generic fallback. I can drop it in the next re-spin if you want.
-Sibi
> > Rob
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