Messages in this thread | | | Date | Tue, 6 Feb 2024 16:01:45 +0100 | From | neil.armstrong@linaro ... | Subject | Re: [PATCHv1 4/5] arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC |
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On 06/02/2024 11:15, Anand Moon wrote: > Hi Neil, > > On Tue, 6 Feb 2024 at 14:30, Neil Armstrong <neil.armstrong@linaro.org> wrote: >> >> On 05/02/2024 18:19, Anand Moon wrote: >>> As per S922X datasheet add missing cache information to the Amlogic >>> S922X SoC. >>> >>> - Each Cortex-A53 core has 32 KB of instruction cache and >>> 32 KB of L1 data cache available. >>> - Each Cortex-A73 core has 64 KB of L1 instruction cache and >>> 64 KB of L1 data cache available. >>> - The little (A53) cluster has 512 KB of unified L2 cache available. >>> - The big (A73) cluster has 1 MB of unified L2 cache available. >> >> Datasheet says: >> The quad core Cortex™-A73 processor is paired with A53 processor in a big.Little configuration, with each >> core has L1 instruction and data chaches, together with a single shared L2 unified cache with A53 >> > Ok, > > Since all the Cortex™-A73 and Cortex™-A53 share some improvements in > the architecture with some improvements in cache features > hence I update the changes accordingly. > Also, I checked this in the ARM documentation earlier on this.
I don't understand, Amlogic states it's a shared L2 cache, but you trust the ARM documentation instead ???
> >> And there's no indication of the L1 or L2 cache sizes. > > What I feel is in general all the Cortex™-A73 and Cortex™-A53 supports > L1 and L2 cache size since it is part of the core features. > but I opted for these size values from a Wikipedia article. > > On my Odroid N2+, I observe the following. > > I have also done some testing on the stress-ng to verify this.
Ok I don't feel confident adding numbers that comes out of thin air, and even more since they are only shared to userspace.
I think we should only add the numbers which are 100% sure
> > alarm@archl-on2:~$ lscpu > Architecture: aarch64 > CPU op-mode(s): 32-bit, 64-bit > Byte Order: Little Endian > CPU(s): 6 > On-line CPU(s) list: 0-5 > Vendor ID: ARM > Model name: Cortex-A53 > Model: 4 > Thread(s) per core: 1 > Core(s) per socket: 2 > Socket(s): 1 > Stepping: r0p4 > CPU(s) scaling MHz: 100% > CPU max MHz: 1800.0000 > CPU min MHz: 1000.0000 > BogoMIPS: 48.00 > Flags: fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid > Model name: Cortex-A73 > Model: 2 > Thread(s) per core: 1 > Core(s) per socket: 4 > Socket(s): 1 > Stepping: r0p2 > CPU(s) scaling MHz: 63% > CPU max MHz: 2208.0000 > CPU min MHz: 1000.0000 > BogoMIPS: 48.00 > Flags: fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid > Caches (sum of all): > L1d: 320 KiB (6 instances) > L1i: 320 KiB (6 instances) > L2: 1.5 MiB (2 instances) > NUMA: > NUMA node(s): 1 > NUMA node0 CPU(s): 0-5 > Vulnerabilities: > Gather data sampling: Not affected > Itlb multihit: Not affected > L1tf: Not affected > Mds: Not affected > Meltdown: Not affected > Mmio stale data: Not affected > Retbleed: Not affected > Spec rstack overflow: Not affected > Spec store bypass: Vulnerable > Spectre v1: Mitigation; __user pointer sanitization > Spectre v2: Vulnerable > Srbds: Not affected > Tsx async abort: Not affected > alarm@archl-on2:~$ > > alarm@archl-on2:~$ lstopo-no-graphics > Machine (3659MB total) > Package L#0 > NUMANode L#0 (P#0 3659MB) > L2 L#0 (512KB) > L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0 + PU L#0 (P#0) > L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1 + PU L#1 (P#1) > L2 L#1 (1024KB) > L1d L#2 (64KB) + L1i L#2 (64KB) + Core L#2 + PU L#2 (P#2) > L1d L#3 (64KB) + L1i L#3 (64KB) + Core L#3 + PU L#3 (P#3) > L1d L#4 (64KB) + L1i L#4 (64KB) + Core L#4 + PU L#4 (P#4) > L1d L#5 (64KB) + L1i L#5 (64KB) + Core L#5 + PU L#5 (P#5) > Block "mmcblk1boot0" > Block "mmcblk1boot1" > Block "mmcblk1" > Net "eth0"
This looks pretty, but let's keep exporting verified data.
> > > >> Neil >> > > Thanks > -Anand
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