Messages in this thread | | | Date | Tue, 6 Feb 2024 12:50:49 +0200 | From | Vladimir Oltean <> | Subject | Re: [PATCH net-next v5 3/7] net: dsa: mt7530: simplify mt7530_pad_clk_setup() |
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On Tue, Feb 06, 2024 at 01:08:04AM +0300, Arınç ÜNAL via B4 Relay wrote: > From: Arınç ÜNAL <arinc.unal@arinc9.com> > > This code is from before this driver was converted to phylink API. Phylink > deals with the unsupported interface cases before mt7530_pad_clk_setup() is > run. Therefore, the default case would never run. However, it must be > defined nonetheless to handle all the remaining enumeration values, the > phy-modes. > > Switch to if statement for RGMII and return which simplifies the code and > saves an indent. > > Set P6_INTF_MODE, which is the three least significant bits of the > MT7530_P6ECR register, to 0 for RGMII even though it will already be 0 > after reset. This is to keep supporting dynamic reconfiguration of the port > in the case the interface changes from TRGMII to RGMII. > > Disable the TRGMII clocks for all cases. They will be enabled if TRGMII is > being used. > > Read XTAL after checking for RGMII as it's only needed for the TRGMII > interface mode. > > Reviewed-by: Daniel Golle <daniel@makrotopia.org> > Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> > Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> > ---
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
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