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    Subject[PATCH] perf: CXL: fix mismatched cpmu event opcode
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    Date
    S2M NDR BI-ConflictAck opcode is described as 4 in the CXL
    3.0 specification. However, it is defined as 3 in macro definition.

    Signed-off-by: Hojin Nam <hj96.nam@samsung.com>
    ---
    drivers/perf/cxl_pmu.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c
    index 365d964b0f6a..bc0d414a6aff 100644
    --- a/drivers/perf/cxl_pmu.c
    +++ b/drivers/perf/cxl_pmu.c
    @@ -419,7 +419,7 @@ static struct attribute *cxl_pmu_event_attrs[] = {
    CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmp, CXL_PMU_GID_S2M_NDR, BIT(0)),
    CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmps, CXL_PMU_GID_S2M_NDR, BIT(1)),
    CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmpe, CXL_PMU_GID_S2M_NDR, BIT(2)),
    - CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_biconflictack, CXL_PMU_GID_S2M_NDR, BIT(3)),
    + CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_biconflictack, CXL_PMU_GID_S2M_NDR, BIT(4)),
    /* CXL rev 3.0 Table 3-46 S2M DRS opcodes */
    CXL_PMU_EVENT_CXL_ATTR(s2m_drs_memdata, CXL_PMU_GID_S2M_DRS, BIT(0)),
    CXL_PMU_EVENT_CXL_ATTR(s2m_drs_memdatanxm, CXL_PMU_GID_S2M_DRS, BIT(1)),
    --
    2.34.1
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