Messages in this thread | | | Date | Tue, 6 Feb 2024 09:54:23 +0100 | From | Neil Armstrong <> | Subject | Re: [PATCHv1 2/5] arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC |
| |
On 05/02/2024 18:19, Anand Moon wrote: > As per S905X3 datasheet add missing cache information to the Amlogic > SM1 SoC. ARM Cortex-A55 CPU uses unified L3 cache instead of L2 cache. > > - Each Cortex-A55 core has 32KB of L1 instruction cache available and > 32KB of L1 data cache available. > - Along with 512KB Unified L3 cache.
This 512K number is for the NPU, AFAIK the CPU L3 Cache size isn't specified in the datasheet
> > To improve system performance. > > Signed-off-by: Anand Moon <linux.amoon@gmail.com> > --- > Datasheet > [0] https://dn.odroid.com/S905X3/ODROID-C4/Docs/S905X3_Public_Datasheet_Hardkernel.pdf > [1] https://en.wikipedia.org/wiki/ARM_Cortex-A55 > --- > arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 39 ++++++++++++++++++---- > 1 file changed, 33 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi > index 643f94d9d08e..403443e782e4 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi > @@ -55,7 +55,13 @@ cpu0: cpu@0 { > compatible = "arm,cortex-a55"; > reg = <0x0 0x0>; > enable-method = "psci"; > - next-level-cache = <&l2>; > + d-cache-line-size = <32>; > + d-cache-size = <0x8000>; > + d-cache-sets = <32>; > + i-cache-line-size = <32>; > + i-cache-size = <0x8000>; > + i-cache-sets = <32>; > + next-level-cache = <&l3>; > #cooling-cells = <2>; > }; > > @@ -64,7 +70,13 @@ cpu1: cpu@1 { > compatible = "arm,cortex-a55"; > reg = <0x0 0x1>; > enable-method = "psci"; > - next-level-cache = <&l2>; > + d-cache-line-size = <32>; > + d-cache-size = <0x8000>; > + d-cache-sets = <32>; > + i-cache-line-size = <32>; > + i-cache-size = <0x8000>; > + i-cache-sets = <32>; > + next-level-cache = <&l3>; > #cooling-cells = <2>; > }; > > @@ -73,7 +85,13 @@ cpu2: cpu@2 { > compatible = "arm,cortex-a55"; > reg = <0x0 0x2>; > enable-method = "psci"; > - next-level-cache = <&l2>; > + d-cache-line-size = <32>; > + d-cache-size = <0x8000>; > + d-cache-sets = <32>; > + i-cache-line-size = <32>; > + i-cache-size = <0x8000>; > + i-cache-sets = <32>; > + next-level-cache = <&l3>; > #cooling-cells = <2>; > }; > > @@ -82,14 +100,23 @@ cpu3: cpu@3 { > compatible = "arm,cortex-a55"; > reg = <0x0 0x3>; > enable-method = "psci"; > - next-level-cache = <&l2>; > + d-cache-line-size = <32>; > + d-cache-size = <0x8000>; > + d-cache-sets = <32>; > + i-cache-line-size = <32>; > + i-cache-size = <0x8000>; > + i-cache-sets = <32>; > + next-level-cache = <&l3>; > #cooling-cells = <2>; > }; > > - l2: l2-cache0 { > + l3: l3-cache0 { > compatible = "cache"; > - cache-level = <2>; > + cache-level = <3>; > cache-unified; > + cache-size = <0x7d000>; /* L2. 512 KB */
Comment should be L3 here
> + cache-line-size = <64>; > + cache-sets = <512>; > }; > }; >
Thanks, Neil
| |