Messages in this thread | | | Date | Tue, 6 Feb 2024 15:58:15 -0600 | Subject | Re: [PATCH v1 2/5] mmc: sdhci_am654: Write ITAPDLY for DDR52 timing | From | Judith Mendez <> |
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Hi Andrew,
On 2/1/24 1:36 PM, Andrew Davis wrote: > On 1/31/24 3:50 PM, Judith Mendez wrote: >> For DDR52 timing, DLL is enabled but tuning is not carried >> out, therefore the ITAPDLY value in PHY CTRL 4 register is >> not correct. Fix this by writing ITAPDLY after enabling DLL. >> >> Fixes: a161c45f2979 ("mmc: sdhci_am654: Enable DLL only for some speed >> modes") >> Signed-off-by: Judith Mendez <jm@ti.com> >> --- >> drivers/mmc/host/sdhci_am654.c | 27 +++++++++++++++------------ >> 1 file changed, 15 insertions(+), 12 deletions(-) >> >> diff --git a/drivers/mmc/host/sdhci_am654.c >> b/drivers/mmc/host/sdhci_am654.c >> index a3798c9912f6..ff18a274b6f2 100644 >> --- a/drivers/mmc/host/sdhci_am654.c >> +++ b/drivers/mmc/host/sdhci_am654.c >> @@ -170,7 +170,19 @@ struct sdhci_am654_driver_data { >> #define DLL_CALIB (1 << 4) >> }; >> -static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned >> int clock) >> +static void sdhci_am654_write_itapdly(struct sdhci_am654_data >> *sdhci_am654, >> + u32 itapdly) > > This patch is confusing, looks like you switched the place of these two > functions, but diff is not really liking that. You can mess with > --diff-algorithm and the like to get a more readable patch. But in > this case why switch their spots at all? > > Seems to be so you can call sdhci_am654_write_itapdly() from > sdhci_am654_setup_dll() without a forward declaration, instead > why not just call sdhci_am654_write_itapdly() after calling > sdhci_am654_setup_dll() below. That also saves to from having > to pass in `timing` to sdhci_am654_write_itapdly() just to > have it pass it right through to sdhci_am654_setup_dll().
Really the only reason I did this is because we call sdhci_am654_write_itapdly() in sdhci_am654_setup_delay_chain and I wanted to keep the flow for setting up DLL the same. I agree the patch looks confusing, so I will fix this for v2.
~ Judith
> Andrew > >> +{ >> + /* Set ITAPCHGWIN before writing to ITAPDLY */ >> + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, >> + 0x1 << ITAPCHGWIN_SHIFT); >> + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, >> + itapdly << ITAPDLYSEL_SHIFT); >> + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, >> 0); >> +} >> + >> +static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned >> int clock, >> + unsigned char timing) >> { >> struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); >> struct sdhci_am654_data *sdhci_am654 = >> sdhci_pltfm_priv(pltfm_host); >> @@ -236,17 +248,8 @@ static void sdhci_am654_setup_dll(struct >> sdhci_host *host, unsigned int clock) >> dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); >> return; >> } >> -} >> -static void sdhci_am654_write_itapdly(struct sdhci_am654_data >> *sdhci_am654, >> - u32 itapdly) >> -{ >> - /* Set ITAPCHGWIN before writing to ITAPDLY */ >> - regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, >> - 1 << ITAPCHGWIN_SHIFT); >> - regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, >> - itapdly << ITAPDLYSEL_SHIFT); >> - regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, >> 0); >> + sdhci_am654_write_itapdly(sdhci_am654, >> sdhci_am654->itap_del_sel[timing]); >> } >> static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data >> *sdhci_am654, >> @@ -298,7 +301,7 @@ static void sdhci_am654_set_clock(struct >> sdhci_host *host, unsigned int clock) >> regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); >> if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) { >> - sdhci_am654_setup_dll(host, clock); >> + sdhci_am654_setup_dll(host, clock, timing); >> sdhci_am654->dll_enable = true; >> } else { >> sdhci_am654_setup_delay_chain(sdhci_am654, timing);
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