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    Subject[PATCH v2 06/18] clk: qcom: gcc-sc8280xp: Set delay for Venus CLK resets
    Some Venus resets may require more time when toggling. Describe that.

    The value was obtained on a best-guess basis: msm-5.4 being the base
    kernel for this SoC and 8280 being generally close to 8350 which is known
    to require a higher delay [1].

    [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98
    Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
    ---
    drivers/clk/qcom/gcc-sc8280xp.c | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c
    index bfb77931e868..9f4db815688c 100644
    --- a/drivers/clk/qcom/gcc-sc8280xp.c
    +++ b/drivers/clk/qcom/gcc-sc8280xp.c
    @@ -7448,8 +7448,8 @@ static const struct qcom_reset_map gcc_sc8280xp_resets[] = {
    [GCC_USB4PHY_PHY_PRIM_BCR] = { 0x4a004 },
    [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
    [GCC_VIDEO_BCR] = { 0x28000 },
    - [GCC_VIDEO_AXI0_CLK_ARES] = { 0x28010, 2 },
    - [GCC_VIDEO_AXI1_CLK_ARES] = { 0x28018, 2 },
    + [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x28010, .bit = 2, .udelay = 400 },
    + [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x28018, .bit = 2, .udelay = 400 },
    };

    static struct gdsc *gcc_sc8280xp_gdscs[] = {
    --
    2.43.0


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