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    Subject[PATCH v2 04/18] clk: qcom: gcc-sa8775p: Set delay for Venus CLK resets
    Some Venus resets may require more time when toggling. Describe that.

    The value was obtained on a best-guess basis: msm-5.4 being the base
    kernel for this SoC and 8775 being generally close to 8350 which is known
    to require a higher delay [1].

    [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98
    Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
    ---
    drivers/clk/qcom/gcc-sa8775p.c | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c
    index 8171d23c96e6..c2b403cb6301 100644
    --- a/drivers/clk/qcom/gcc-sa8775p.c
    +++ b/drivers/clk/qcom/gcc-sa8775p.c
    @@ -4662,8 +4662,8 @@ static const struct qcom_reset_map gcc_sa8775p_resets[] = {
    [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x5c020 },
    [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x5c024 },
    [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x76000 },
    - [GCC_VIDEO_AXI0_CLK_ARES] = { 0x34014, 2 },
    - [GCC_VIDEO_AXI1_CLK_ARES] = { 0x3401c, 2 },
    + [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x34014, .bit = 2, .udelay = 400 },
    + [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x3401c, .bit = 2, .udelay = 400 },
    [GCC_VIDEO_BCR] = { 0x34000 },
    };

    --
    2.43.0


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