Messages in this thread | | | Date | Tue, 27 Feb 2024 12:56:59 -0800 (PST) | Subject | Re: [PATCH v2,RESEND 1/2] drivers: perf: added capabilities for legacy PMU | From | Palmer Dabbelt <> |
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On Tue, 27 Feb 2024 11:26:20 PST (-0800), alex@ghiti.fr wrote: > On 27/02/2024 18:00, Vadim Shakirov wrote: >> Added the PERF_PMU_CAP_NO_INTERRUPT flag because the legacy pmu driver >> does not provide sampling capabilities >> >> Added the PERF_PMU_CAP_NO_EXCLUDE flag because the legacy pmu driver >> does not provide the ability to disable counter incrementation in >> different privilege modes >> >> Suggested-by: Atish Patra <atishp@rivosinc.com> >> Signed-off-by: Vadim Shakirov <vadim.shakirov@syntacore.com> >> --- >> drivers/perf/riscv_pmu_legacy.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legacy.c >> index 79fdd667922e..a85fc9a15f03 100644 >> --- a/drivers/perf/riscv_pmu_legacy.c >> +++ b/drivers/perf/riscv_pmu_legacy.c >> @@ -117,6 +117,8 @@ static void pmu_legacy_init(struct riscv_pmu *pmu) >> pmu->event_mapped = pmu_legacy_event_mapped; >> pmu->event_unmapped = pmu_legacy_event_unmapped; >> pmu->csr_index = pmu_legacy_csr_index; >> + pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; >> + pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE; >> >> perf_pmu_register(&pmu->pmu, "cpu", PERF_TYPE_RAW); >> } > > > I see here that Atish added its RB: > https://lore.kernel.org/linux-riscv/CAOnJCUJ-eE+zbXH0yBX_QBK2ep779q=wNCSrc+BJfzUb+zBCaw@mail.gmail.com/ > > So I add it here (hopefully b4 won't complain, I don't know): > > Reviewed-by: Atish Patra <atishp@rivosinc.com>
It says
NOTE: some trailers ignored due to from/email mismatches: ! Trailer: Reviewed-by: Atish Patra <atishp@rivosinc.com> Msg From: Alexandre Ghiti <alex@ghiti.fr> NOTE: Rerun with -S to apply them anyway
Should show up on fixes in a bit, assuming it gets through the testing.
> > And I'd say the fixes tag for this one is: > > Fixes: 9b3e150e310e ("RISC-V: Add a simple platform driver for RISC-V > legacy perf") > > Thanks, > > Alex
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