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    Subject[PATCH v19 051/130] KVM: x86/mmu: Add Suppress VE bit to shadow_mmio_mask/shadow_present_mask
    Date
    From: Isaku Yamahata <isaku.yamahata@intel.com>

    To make use of the same value of shadow_mmio_mask and shadow_present_mask
    for TDX and VMX, add Suppress-VE bit to shadow_mmio_mask and
    shadow_present_mask so that they can be common for both VMX and TDX.

    TDX will require shadow_mmio_mask and shadow_present_mask to include
    VMX_SUPPRESS_VE for shared GPA so that EPT violation is triggered for
    shared GPA. For VMX, VMX_SUPPRESS_VE doesn't matter for MMIO because the
    spte value is required to cause EPT misconfig. the additional bit doesn't
    affect VMX logic to add the bit to shadow_mmio_{value, mask}.

    Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
    ---
    arch/x86/include/asm/vmx.h | 1 +
    arch/x86/kvm/mmu/spte.c | 6 ++++--
    2 files changed, 5 insertions(+), 2 deletions(-)

    diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
    index 0e73616b82f3..76ed39541a52 100644
    --- a/arch/x86/include/asm/vmx.h
    +++ b/arch/x86/include/asm/vmx.h
    @@ -513,6 +513,7 @@ enum vmcs_field {
    #define VMX_EPT_IPAT_BIT (1ull << 6)
    #define VMX_EPT_ACCESS_BIT (1ull << 8)
    #define VMX_EPT_DIRTY_BIT (1ull << 9)
    +#define VMX_EPT_SUPPRESS_VE_BIT (1ull << 63)
    #define VMX_EPT_RWX_MASK (VMX_EPT_READABLE_MASK | \
    VMX_EPT_WRITABLE_MASK | \
    VMX_EPT_EXECUTABLE_MASK)
    diff --git a/arch/x86/kvm/mmu/spte.c b/arch/x86/kvm/mmu/spte.c
    index 4a599130e9c9..02a466de2991 100644
    --- a/arch/x86/kvm/mmu/spte.c
    +++ b/arch/x86/kvm/mmu/spte.c
    @@ -429,7 +429,9 @@ void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only)
    shadow_dirty_mask = has_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull;
    shadow_nx_mask = 0ull;
    shadow_x_mask = VMX_EPT_EXECUTABLE_MASK;
    - shadow_present_mask = has_exec_only ? 0ull : VMX_EPT_READABLE_MASK;
    + /* VMX_EPT_SUPPRESS_VE_BIT is needed for W or X violation. */
    + shadow_present_mask =
    + (has_exec_only ? 0ull : VMX_EPT_READABLE_MASK) | VMX_EPT_SUPPRESS_VE_BIT;
    /*
    * EPT overrides the host MTRRs, and so KVM must program the desired
    * memtype directly into the SPTEs. Note, this mask is just the mask
    @@ -446,7 +448,7 @@ void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only)
    * of an EPT paging-structure entry is 110b (write/execute).
    */
    kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE,
    - VMX_EPT_RWX_MASK, 0);
    + VMX_EPT_RWX_MASK | VMX_EPT_SUPPRESS_VE_BIT, 0);
    }
    EXPORT_SYMBOL_GPL(kvm_mmu_set_ept_masks);

    --
    2.25.1

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