Messages in this thread | | | Date | Mon, 26 Feb 2024 20:09:26 +0100 | From | Dragan Simic <> | Subject | Re: [PATCH v1] arm64: dts: rockchip: Add cache information to the Rockchip RK3566 and RK3568 SoC |
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Hello Anand,
On 2024-02-26 19:23, Anand Moon wrote: > As per RK3568 Datasheet and TRM add missing cache information to > the Rockchip RK3566 and RK3568 SoC. > > - Each Cortex-A55 core has 32KB of L1 instruction cache available and > 32KB of L1 data cache available with ECC. > - Along with 512KB Unified L3 cache with ECC. > > With adding instruction cache and data cache and a write buffer to > reduce the effect of main memory bandwidth and latency on data > access performance. > > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
I was about to send my own patch that adds the same missing cache information, so please allow me to describe the proposed way to move forward.
The way I see it, your commit summary and description need a rather complete rewrite, to be more readable, more accurate, and to avoid including an irrelevant (and slightly misleading) description of the general role of caches.
Also, the changes to the dtsi file would benefit from small touch-ups here and there, for improved consistency, etc.
With all that in mind, I propose that you withdraw your patch and let me send my patch that will addresses all these issues, of course with a proper tag that lists you as a co-developer. I think that would save us a fair amount of time going back and forth.
I hope you agree.
> --- > [0] > http://www.rock-chips.com/uploads/pdf/2022.8.26/191/RK3568%20Brief%20Datasheet.pdf > [1] > https://dl.radxa.com/rock3/docs/hw/datasheet/Rockchip%20RK3568%20TRM%20Part1%20V1.1-20210301.pdf > --- > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 37 ++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > index c19c0f1b3778..49235efefb6b 100644 > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > @@ -56,6 +56,13 @@ cpu0: cpu@0 { > clocks = <&scmi_clk 0>; > #cooling-cells = <2>; > enable-method = "psci"; > + d-cache-line-size = <32>; > + d-cache-size = <0x8000>; > + d-cache-sets = <32>; > + i-cache-line-size = <32>; > + i-cache-size = <0x8000>; > + i-cache-sets = <32>; > + next-level-cache = <&l2>; > operating-points-v2 = <&cpu0_opp_table>; > }; > > @@ -65,6 +72,13 @@ cpu1: cpu@100 { > reg = <0x0 0x100>; > #cooling-cells = <2>; > enable-method = "psci"; > + d-cache-line-size = <32>; > + d-cache-size = <0x8000>; > + d-cache-sets = <32>; > + i-cache-line-size = <32>; > + i-cache-size = <0x8000>; > + i-cache-sets = <32>; > + next-level-cache = <&l2>; > operating-points-v2 = <&cpu0_opp_table>; > }; > > @@ -74,6 +88,13 @@ cpu2: cpu@200 { > reg = <0x0 0x200>; > #cooling-cells = <2>; > enable-method = "psci"; > + d-cache-line-size = <32>; > + d-cache-size = <0x8000>; > + d-cache-sets = <32>; > + i-cache-line-size = <32>; > + i-cache-size = <0x8000>; > + i-cache-sets = <32>; > + next-level-cache = <&l2>; > operating-points-v2 = <&cpu0_opp_table>; > }; > > @@ -83,8 +104,24 @@ cpu3: cpu@300 { > reg = <0x0 0x300>; > #cooling-cells = <2>; > enable-method = "psci"; > + d-cache-line-size = <32>; > + d-cache-size = <0x8000>; > + d-cache-sets = <32>; > + i-cache-line-size = <32>; > + i-cache-size = <0x8000>; > + i-cache-sets = <32>; > + next-level-cache = <&l2>; > operating-points-v2 = <&cpu0_opp_table>; > }; > + > + l2: l2-cache0 { > + compatible = "cache"; > + cache-level = <3>; > + cache-unified; > + cache-size = <0x7d000>; /* L3. 512 KB */ > + cache-line-size = <64>; > + cache-sets = <512>; > + }; > }; > > cpu0_opp_table: opp-table-0 {
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