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    Subject[RESEND v6 7/9] arm64: dts: imx93: add usb nodes
    Date
    There are 2 USB controllers on i.MX93. Add them.

    Acked-by: Alexander Stein <alexander.stein@ew.tq-group.com>
    Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> # TQMa9352LA/CA
    Signed-off-by: Xu Yang <xu.yang_2@nxp.com>

    ---
    Changes in v2:
    - fix format as suggested by Alexander
    - change compatible from fsl,imx8mm-usb to fsl,imx93-usb
    Changes in v3:
    - replace deprecated fsl,usbphy with phys as suggested by Alexander
    - reorder nodes
    Changes in v4:
    - fix the alignment
    Changes in v5:
    - rename usb_wakeup_clk to usb_wakeup
    Changes in v6:
    - rename usb_ctrl_root_clk to usb_ctrl_root
    ---
    arch/arm64/boot/dts/freescale/imx93.dtsi | 58 ++++++++++++++++++++++++
    1 file changed, 58 insertions(+)

    diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
    index 8f2e7c42ad6e..4a7efccb4f67 100644
    --- a/arch/arm64/boot/dts/freescale/imx93.dtsi
    +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
    @@ -183,6 +183,20 @@ mqs2: mqs2 {
    status = "disabled";
    };

    + usbphynop1: usbphynop1 {
    + compatible = "usb-nop-xceiv";
    + #phy-cells = <0>;
    + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
    + clock-names = "main_clk";
    + };
    +
    + usbphynop2: usbphynop2 {
    + compatible = "usb-nop-xceiv";
    + #phy-cells = <0>;
    + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
    + clock-names = "main_clk";
    + };
    +
    soc@0 {
    compatible = "simple-bus";
    #address-cells = <1>;
    @@ -1167,6 +1181,50 @@ media_blk_ctrl: system-controller@4ac10000 {
    status = "disabled";
    };

    + usbotg1: usb@4c100000 {
    + compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
    + reg = <0x4c100000 0x200>;
    + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
    + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>,
    + <&clk IMX93_CLK_HSIO_32K_GATE>;
    + clock-names = "usb_ctrl_root", "usb_wakeup";
    + assigned-clocks = <&clk IMX93_CLK_HSIO>;
    + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
    + assigned-clock-rates = <133000000>;
    + phys = <&usbphynop1>;
    + fsl,usbmisc = <&usbmisc1 0>;
    + status = "disabled";
    + };
    +
    + usbmisc1: usbmisc@4c100200 {
    + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
    + "fsl,imx6q-usbmisc";
    + reg = <0x4c100200 0x200>;
    + #index-cells = <1>;
    + };
    +
    + usbotg2: usb@4c200000 {
    + compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
    + reg = <0x4c200000 0x200>;
    + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
    + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>,
    + <&clk IMX93_CLK_HSIO_32K_GATE>;
    + clock-names = "usb_ctrl_root", "usb_wakeup";
    + assigned-clocks = <&clk IMX93_CLK_HSIO>;
    + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
    + assigned-clock-rates = <133000000>;
    + phys = <&usbphynop2>;
    + fsl,usbmisc = <&usbmisc2 0>;
    + status = "disabled";
    + };
    +
    + usbmisc2: usbmisc@4c200200 {
    + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
    + "fsl,imx6q-usbmisc";
    + reg = <0x4c200200 0x200>;
    + #index-cells = <1>;
    + };
    +
    ddr-pmu@4e300dc0 {
    compatible = "fsl,imx93-ddr-pmu";
    reg = <0x4e300dc0 0x200>;
    --
    2.34.1

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