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    Subject[PATCH 17/21] ARM: dts: qcom: ipq8064: Add PCIe bridge node
    On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
    for each controller instance. Hence, add a node to represent the bridge.

    Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
    ---
    arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 30 ++++++++++++++++++++++++++++++
    1 file changed, 30 insertions(+)

    diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
    index 6a7f4dd0f775..98448ea6ffca 100644
    --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
    +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
    @@ -1125,6 +1125,16 @@ pcie0: pcie@1b500000 {

    status = "disabled";
    perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
    +
    + pcie@0 {
    + device_type = "pci";
    + reg = <0x0 0x0 0x0 0x0 0x0>;
    + bus-range = <0x01 0xff>;
    +
    + #address-cells = <3>;
    + #size-cells = <2>;
    + ranges;
    + };
    };

    pcie1: pcie@1b700000 {
    @@ -1176,6 +1186,16 @@ pcie1: pcie@1b700000 {

    status = "disabled";
    perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
    +
    + pcie@0 {
    + device_type = "pci";
    + reg = <0x0 0x0 0x0 0x0 0x0>;
    + bus-range = <0x01 0xff>;
    +
    + #address-cells = <3>;
    + #size-cells = <2>;
    + ranges;
    + };
    };

    pcie2: pcie@1b900000 {
    @@ -1227,6 +1247,16 @@ pcie2: pcie@1b900000 {

    status = "disabled";
    perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
    +
    + pcie@0 {
    + device_type = "pci";
    + reg = <0x0 0x0 0x0 0x0 0x0>;
    + bus-range = <0x01 0xff>;
    +
    + #address-cells = <3>;
    + #size-cells = <2>;
    + ranges;
    + };
    };

    qsgmii_csr: syscon@1bb00000 {
    --
    2.25.1


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