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    Subject[PATCH 15/21] arm64: dts: qcom: ipq8074: Add PCIe bridge node
    On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
    for each controller instance. Hence, add a node to represent the bridge.

    Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
    ---
    arch/arm64/boot/dts/qcom/ipq8074.dtsi | 20 ++++++++++++++++++++
    1 file changed, 20 insertions(+)

    diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
    index cf295bed3299..ae1677362421 100644
    --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
    +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
    @@ -848,6 +848,16 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
    "ahb",
    "axi_m_sticky";
    status = "disabled";
    +
    + pcie@0 {
    + device_type = "pci";
    + reg = <0x0 0x0 0x0 0x0 0x0>;
    + bus-range = <0x01 0xff>;
    +
    + #address-cells = <3>;
    + #size-cells = <2>;
    + ranges;
    + };
    };

    pcie0: pcie@20000000 {
    @@ -913,6 +923,16 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
    "axi_m_sticky",
    "axi_s_sticky";
    status = "disabled";
    +
    + pcie@0 {
    + device_type = "pci";
    + reg = <0x0 0x0 0x0 0x0 0x0>;
    + bus-range = <0x01 0xff>;
    +
    + #address-cells = <3>;
    + #size-cells = <2>;
    + ranges;
    + };
    };
    };

    --
    2.25.1


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