Messages in this thread | | | Date | Fri, 2 Feb 2024 13:37:56 +0200 | Subject | Re: [PATCH v4 2/5] phy: cadence-torrent: Add PCIe(100MHz) + USXGMII(156.25MHz) multilink configuration | From | Roger Quadros <> |
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On 04/01/2024 15:30, Swapnil Jakhade wrote: > Torrent PHY can have separate input reference clocks for PLL0 and PLL1. > Add support for dual reference clock multilink configurations. > > Add register sequences for PCIe(100MHz) + USXGMII(156.25MHz) multilink > configuration. PCIe uses PLL0 and USXGMII uses PLL1. > > Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
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