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    Subject[PATCH net-next v3 5/7] net: dsa: mt7530: simplify mt7530_setup_port6() and change to void
    From: Arınç ÜNAL <arinc.unal@arinc9.com>

    This code is from before this driver was converted to phylink API. Phylink
    deals with the unsupported interface cases before mt7530_setup_port6() is
    run. Therefore, the default case would never run. However, it must be
    defined nonetheless to handle all the remaining enumeration values, the
    phy-modes.

    Switch to if statement for RGMII and return which simplifies the code and
    saves an indent.

    Set P6_INTF_MODE, which is the the three least significant bits of the
    MT7530_P6ECR register, to 0 for RGMII even though it will already be 0
    after reset. This is to keep supporting dynamic reconfiguration of the port
    in the case the interface changes from TRGMII to RGMII.

    Disable the TRGMII clocks for all cases. They will be enabled if TRGMII is
    being used.

    Read XTAL after checking for RGMII as it's only needed for the TRGMII
    interface mode.

    Change mt7530_setup_port6() to void now that there're no error cases left.

    Reviewed-by: Daniel Golle <daniel@makrotopia.org>
    Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
    ---
    drivers/net/dsa/mt7530.c | 101 ++++++++++++++++++++---------------------------
    1 file changed, 42 insertions(+), 59 deletions(-)

    diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
    index c4d492e29fdf..e1fdef5766fb 100644
    --- a/drivers/net/dsa/mt7530.c
    +++ b/drivers/net/dsa/mt7530.c
    @@ -414,70 +414,57 @@ mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds)
    }

    /* Setup port 6 interface mode and TRGMII TX circuit */
    -static int
    +static void
    mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface)
    {
    struct mt7530_priv *priv = ds->priv;
    - u32 ncpo1, ssc_delta, trgint, xtal;
    + u32 ncpo1, ssc_delta, xtal;

    - xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
    + /* Disable the MT7530 TRGMII clocks */
    + core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);

    - switch (interface) {
    - case PHY_INTERFACE_MODE_RGMII:
    - trgint = 0;
    - break;
    - case PHY_INTERFACE_MODE_TRGMII:
    - trgint = 1;
    - if (xtal == HWTRAP_XTAL_25MHZ)
    - ssc_delta = 0x57;
    - else
    - ssc_delta = 0x87;
    - if (priv->id == ID_MT7621) {
    - /* PLL frequency: 125MHz: 1.0GBit */
    - if (xtal == HWTRAP_XTAL_40MHZ)
    - ncpo1 = 0x0640;
    - if (xtal == HWTRAP_XTAL_25MHZ)
    - ncpo1 = 0x0a00;
    - } else { /* PLL frequency: 250MHz: 2.0Gbit */
    - if (xtal == HWTRAP_XTAL_40MHZ)
    - ncpo1 = 0x0c80;
    - if (xtal == HWTRAP_XTAL_25MHZ)
    - ncpo1 = 0x1400;
    - }
    - break;
    - default:
    - dev_err(priv->dev, "xMII interface %d not supported\n",
    - interface);
    - return -EINVAL;
    + if (interface == PHY_INTERFACE_MODE_RGMII) {
    + mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
    + P6_INTF_MODE(0));
    + return;
    }

    - mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
    - P6_INTF_MODE(trgint));
    + mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1));

    - if (trgint) {
    - /* Disable the MT7530 TRGMII clocks */
    - core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
    + xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;

    - /* Setup the MT7530 TRGMII Tx Clock */
    - core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
    - core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
    - core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
    - core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
    - core_write(priv, CORE_PLL_GROUP4,
    - RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
    - RG_SYSPLL_BIAS_LPF_EN);
    - core_write(priv, CORE_PLL_GROUP2,
    - RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
    - RG_SYSPLL_POSDIV(1));
    - core_write(priv, CORE_PLL_GROUP7,
    - RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
    - RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
    + if (xtal == HWTRAP_XTAL_25MHZ)
    + ssc_delta = 0x57;
    + else
    + ssc_delta = 0x87;

    - /* Enable the MT7530 TRGMII clocks */
    - core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
    + if (priv->id == ID_MT7621) {
    + /* PLL frequency: 125MHz: 1.0GBit */
    + if (xtal == HWTRAP_XTAL_40MHZ)
    + ncpo1 = 0x0640;
    + if (xtal == HWTRAP_XTAL_25MHZ)
    + ncpo1 = 0x0a00;
    + } else { /* PLL frequency: 250MHz: 2.0Gbit */
    + if (xtal == HWTRAP_XTAL_40MHZ)
    + ncpo1 = 0x0c80;
    + if (xtal == HWTRAP_XTAL_25MHZ)
    + ncpo1 = 0x1400;
    }

    - return 0;
    + /* Setup the MT7530 TRGMII Tx Clock */
    + core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
    + core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
    + core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
    + core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
    + core_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN |
    + RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN);
    + core_write(priv, CORE_PLL_GROUP2, RG_SYSPLL_EN_NORMAL |
    + RG_SYSPLL_VODEN | RG_SYSPLL_POSDIV(1));
    + core_write(priv, CORE_PLL_GROUP7, RG_LCDDS_PCW_NCPO_CHG |
    + RG_LCCDS_C(3) | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
    +
    + /* Enable the MT7530 TRGMII clocks */
    + core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
    }

    static void
    @@ -2609,15 +2596,11 @@ mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
    phy_interface_t interface)
    {
    struct mt7530_priv *priv = ds->priv;
    - int ret;

    - if (port == 5) {
    + if (port == 5)
    mt7530_setup_port5(priv->ds, interface);
    - } else if (port == 6) {
    - ret = mt7530_setup_port6(priv->ds, interface);
    - if (ret)
    - return ret;
    - }
    + else if (port == 6)
    + mt7530_setup_port6(priv->ds, interface);

    return 0;
    }
    --
    2.40.1


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