Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Fri, 16 Feb 2024 15:10:04 +0100 | Subject | Re: [PATCH 10/17] clk: renesas: r9a08g045: Add support for power domains |
| |
Hi Claudiu,
On Thu, Feb 8, 2024 at 1:44 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Instantiate power domains for the currently enabled IPs of R9A08G045 SoC. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/clk/renesas/r9a08g045-cpg.c > +++ b/drivers/clk/renesas/r9a08g045-cpg.c > @@ -240,6 +240,28 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { > MOD_CLK_BASE + R9A08G045_DMAC_ACLK, > }; > > +static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { > + DEF_PD("always-on", R9A08G045_PD_ALWAYS_ON, 0, 0, > + RZG2L_PD_F_PARENT | RZG2L_PD_F_ALWAYS_ON), > + DEF_PD("gic", R9A08G045_PD_GIC, MSTOP(ACPU, BIT(3)), PWRDN(IP1, 2),
My docs document only bit 0 of the CPG_BUS_ACPU_MSTOP register.
> + RZG2L_PD_F_ALWAYS_ON), > + DEF_PD("ia55", R9A08G045_PD_IA55, MSTOP(PERI_CPU, BIT(13)), PWRDN(IP1, 3), > + RZG2L_PD_F_ALWAYS_ON), > + DEF_PD("dmac", R9A08G045_PD_DMAC, MSTOP(REG1, GENMASK(3, 0)), 0, > + RZG2L_PD_F_ALWAYS_ON), > + DEF_PD("ddr", R9A08G045_PD_DDR, MSTOP(PERI_DDR, BIT(1)), PWRDN(IP2, 0),
Only BIT(1)? My docs suggest GENMASK(1, 0).
> + RZG2L_PD_F_ALWAYS_ON), > + DEF_PD("tzcddr", R9A08G045_PD_TZCDDR, MSTOP(TZCDDR, GENMASK(2, 0)), > + PWRDN(IP2, 1), RZG2L_PD_F_ALWAYS_ON), > + DEF_PD("otfde_ddr", R9A08G045_PD_OTFDE_DDR, 0, PWRDN(IP2, 2), RZG2L_PD_F_ALWAYS_ON),
MSTOP(PERI_CPU2, BIT(2))?
> + DEF_PD("sdhi0", R9A08G045_PD_SDHI0, MSTOP(PERI_COM, BIT(0)), PWRDN(IP1, 13), 0), > + DEF_PD("sdhi1", R9A08G045_PD_SDHI1, MSTOP(PERI_COM, BIT(1)), PWRDN(IP1, 14), 0), > + DEF_PD("sdhi2", R9A08G045_PD_SDHI2, MSTOP(PERI_COM, BIT(11)), PWRDN(IP1, 15), 0), > + DEF_PD("eth0", R9A08G045_PD_ETHER0, MSTOP(PERI_COM, BIT(2)), PWRDN(IP1, 11), 0), > + DEF_PD("eth1", R9A08G045_PD_ETHER1, MSTOP(PERI_COM, BIT(3)), PWRDN(IP1, 12), 0), > + DEF_PD("scif0", R9A08G045_PD_SCIF0, MSTOP(MCPU2, BIT(1)), 0, 0), > +}; > +
The rest LGTM.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68korg
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
| |