Messages in this thread Patch in this message | | | From | Tudor Ambarus <> | Subject | [PATCH v2 3/7] ARM: dts: samsung: exynos5250: specify the SPI FIFO depth | Date | Fri, 16 Feb 2024 14:04:45 +0000 |
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Up to now the SPI alias was used as an index into an array defined in the SPI driver to determine the SPI FIFO depth. Drop the dependency on the SPI alias and specify the SPI FIFO depth directly into the SPI node.
exynos5250.dtsi defines the following aliases: spi0 = &spi_0; spi1 = &spi_1; spi2 = &spi_2; spi-s3c64xx.c driver defines the following fifo_lvl_mask for the "samsung,exynos4210-spi" compatible: .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, Thus spi0 was considered having a 256 byte FIFO depth, and spi1 and spi2 having 64 byte FIFO depth each. Update device tree with these FIFO depths. No functional change expected.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> --- arch/arm/boot/dts/samsung/exynos5250.dtsi | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/samsung/exynos5250.dtsi b/arch/arm/boot/dts/samsung/exynos5250.dtsi index 99c84bebf25a..b9e7c4938818 100644 --- a/arch/arm/boot/dts/samsung/exynos5250.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5250.dtsi @@ -511,6 +511,7 @@ spi_0: spi@12d20000 { clock-names = "spi", "spi_busclk0"; pinctrl-names = "default"; pinctrl-0 = <&spi0_bus>; + fifo-depth = <256>; }; spi_1: spi@12d30000 { @@ -526,6 +527,7 @@ spi_1: spi@12d30000 { clock-names = "spi", "spi_busclk0"; pinctrl-names = "default"; pinctrl-0 = <&spi1_bus>; + fifo-depth = <64>; }; spi_2: spi@12d40000 { @@ -541,6 +543,7 @@ spi_2: spi@12d40000 { clock-names = "spi", "spi_busclk0"; pinctrl-names = "default"; pinctrl-0 = <&spi2_bus>; + fifo-depth = <64>; }; mmc_0: mmc@12200000 { -- 2.44.0.rc0.258.g7320e95886-goog
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