Messages in this thread | | | Date | Fri, 16 Feb 2024 07:45:11 +0900 | Subject | Re: [PATCH v2] ata: ahci_ceva: fix error handling for Xilinx GT PHY support | From | Damien Le Moal <> |
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On 2/16/24 03:01, Radhey Shyam Pandey wrote: > Platform clock and phy error resources are not cleaned up in Xilinx GT PHY > error path. > > To fix it create a wrapper ceva_ahci_platform_enable_resources() API which
create a wrapper ceva_ahci_platform_enable_resources() API -> introduce the function ceva_ahci_platform_enable_resources()
> is a customized version of ahci_platform_enable_resources() and inline with > SATA IP programming sequence it does: > > - Assert SATA reset > - Program PS GTR phy > - Bring SATA by de-asserting the reset > - Wait for GT lane PLL to be locked > > It switches to ceva_ahci_platform_enable_resources() in resume path > as same SATA programming sequence (as in probe) should be followed.
What is "It" ?
> It also cleanup mix usage of ahci_platform_enable_resources() and custom > implementation in probe function as both are not required.
Same here, but may be "It" == "this commit" ? If that is the case, then simply rewrite your sentences simply like:
ceva_ahci_platform_enable_resources() is also used in the resume path as the same SATA programming sequence (as in probe) should be followed. Also cleanup the mixed usage of ahci_platform_enable_resources() and custom implementation in the probe function as both are not required.
> Fixes: 9a9d3abe24bb ("ata: ahci: ceva: Update the driver to support xilinx GT phy") > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Other than these nits, this looks OK to me.
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
-- Damien Le Moal Western Digital Research
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