Messages in this thread | | | Date | Fri, 16 Feb 2024 21:53:02 +0100 | From | Dimitri Fedrau <> | Subject | Re: Re: [PATCH v6 net-next 05/14] net: phy: marvell-88q2xxx: add driver for the Marvell 88Q2220 PHY |
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Am Fri, Feb 16, 2024 at 10:18:10AM +0100 schrieb Gregor Herburger: > On Thu, Feb 15, 2024 at 09:24:03PM +0100, Dimitri Fedrau wrote: > > > Hi Dimitri, > > > > > Hi Gregor, > > > > > On Tue, Feb 13, 2024 at 10:39:44PM +0100, Dimitri Fedrau wrote: > > > > static struct phy_driver mv88q2xxx_driver[] = { > > > > { > > > > .phy_id = MARVELL_PHY_ID_88Q2110, > > > > @@ -255,12 +439,26 @@ static struct phy_driver mv88q2xxx_driver[] = { > > > > .get_sqi = mv88q2xxx_get_sqi, > > > > .get_sqi_max = mv88q2xxx_get_sqi_max, > > > > }, > > > > + { > > > > + PHY_ID_MATCH_EXACT(PHY_ID_88Q2220_REVB0), > > > > > > I tested the series on a 88Q2220 REV B1 (which is id 0x002b0b22). The > > > driver works fine on this revision. > > > > > > I understand that in the Marvell API the initialization for Rev B0 and > > > B1 differ. For B0 some additional init sequence is executed. I did not look > > > into the details of this sequence. However this patch seems to work on > > > Rev B1. > > > > > > Would you consider adding compatibility for Rev B1 and following? I > > > tested with: > > > .phy_id = MARVELL_PHY_ID_88Q2220, > > > .phy_id_mask = MARVELL_PHY_ID_MASK, > > > > > > > thanks for testing. I would stick to the exact initialization sequence > > provided by the Marvell API. Registers and bits are mostly undocumented > > and I think it is safest this way. Besides that it should be relatively > > easy to add the support for rev. B1 by just adding the init sequence for > > it. > > Ok. I will have an closer look at the marvell API and eventually come up > with a patch for Rev. B1. > > There is also a Rev.B2 for which I cannot find any init sequence. But > Rev. B1 will no longer be produced so I need a solution for B2 > eventually. > After having a quick glance at the latest Marvell API release, the init sequences for B1 and B2 are almost the same. It differs by a single register write. Would be great if you can come up with a patch.
Dimitri
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