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SubjectRe: [PATCH v2 2/7] mmc: sdhci_am654: Write ITAPDLY for DDR52 timing
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On 2/6/24 7:15 PM, Judith Mendez wrote:
> For DDR52 timing, DLL is enabled but tuning is not carried
> out, therefore the ITAPDLY value in PHY CTRL 4 register is
> not correct. Fix this by writing ITAPDLY after enabling DLL.
>
> Fixes: a161c45f2979 ("mmc: sdhci_am654: Enable DLL only for some speed modes")
> Signed-off-by: Judith Mendez <jm@ti.com>
> ---
> Changelog:
> v1->v2:
> - Call sdhci_am654_write_itapdly() in sdhci_am654_set_clock()
> instead of sdhci_am654_setup_dll()
> ---
> drivers/mmc/host/sdhci_am654.c | 1 +
> 1 file changed, 1 insertion(+)

See how much easier this patch is this way :)

Reviewed-by: Andrew Davis <afd@ti.com>

>
> diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
> index 2c66a965c225..b50db5d4a452 100644
> --- a/drivers/mmc/host/sdhci_am654.c
> +++ b/drivers/mmc/host/sdhci_am654.c
> @@ -299,6 +299,7 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
>
> if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) {
> sdhci_am654_setup_dll(host, clock);
> + sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing]);
> sdhci_am654->dll_enable = true;
> } else {
> sdhci_am654_setup_delay_chain(sdhci_am654, timing);

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