Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Mon, 12 Feb 2024 15:01:05 +0100 | Subject | Re: [PATCH 1/2] clk: renesas: r9a08g04{3,4}: Use SEL_SDHI1_STS status configuration for SD1 mux |
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On Thu, Feb 1, 2024 at 9:46 AM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > The status configuration for SD1 mux clock is SEL_SDHI1_STS. Fix it. > > Fixes: 16b86e5c03c5 ("clk: renesas: rzg2l: Refactor SD mux driver") > Reported-by: Hien Huynh <hien.huynh.px@renesas.com> > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk for v6.9, with s/r9a08/r9a07/.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68korg
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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