Messages in this thread Patch in this message | | | From | Théo Lebrun <> | Date | Mon, 12 Feb 2024 14:44:43 +0100 | Subject | [PATCH v6 12/13] MIPS: mobileye: eyeq5: add OLB reset controller node |
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Add the devicetree node for the reset controller on the Mobileye EyeQ5 platform. It appears as a subnode to the OLB syscon as its registers are located in this shared register region.
Add reset phandles to UART nodes.
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index 1a65b43e13b1..76935f237ab5 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -78,6 +78,7 @@ uart0: serial@800000 { interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>; clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; + resets = <&reset 0 10>; }; uart1: serial@900000 { @@ -88,6 +89,7 @@ uart1: serial@900000 { interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>; clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; + resets = <&reset 0 11>; }; uart2: serial@a00000 { @@ -98,6 +100,7 @@ uart2: serial@a00000 { interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>; clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; + resets = <&reset 0 12>; }; olb: system-controller@e00000 { @@ -107,6 +110,13 @@ olb: system-controller@e00000 { #address-cells = <1>; #size-cells = <1>; + reset: reset-controller@e00000 { + compatible = "mobileye,eyeq5-reset"; + reg = <0x000 0x0c>, <0x200 0x34>, <0x120 0x04>; + reg-names = "d0", "d1", "d2"; + #reset-cells = <2>; + }; + clocks: clock-controller@e0002c { compatible = "mobileye,eyeq5-clk"; reg = <0x02c 0x50>, <0x11c 0x04>; -- 2.43.0
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