Messages in this thread Patch in this message | ![/](/images/icornerl.gif) | | From | Claudiu <> | Subject | [PATCH v2 10/11] arm64: dts: renesas: r9a08g045: Add watchdog node | Date | Wed, 31 Jan 2024 12:20:16 +0200 |
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From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Add the DT node for the watchdog IP accessible by Cortex-A of RZ/G3S SoC (R9108G045).
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> ---
Changes in v2: - collected tags
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 5facfad96158..dfee878c0f49 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -264,6 +264,20 @@ gic: interrupt-controller@12400000 { <0x0 0x12440000 0 0x60000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; }; + + wdt0: watchdog@12800800 { + compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt"; + reg = <0 0x12800800 0 0x400>; + clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>, + <&cpg CPG_MOD R9A08G045_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A08G045_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; }; timer { -- 2.39.2
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