Messages in this thread | | | Date | Wed, 6 Sep 2023 09:13:32 +0200 | From | Andrew Jones <> | Subject | Re: [PATCH v2 3/8] tools: riscv: Add header file csr.h |
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On Wed, Sep 06, 2023 at 02:35:42PM +0800, Haibo Xu wrote: > On Mon, Sep 4, 2023 at 9:33 PM Andrew Jones <ajones@ventanamicro.com> wrote: > > > > On Sat, Sep 02, 2023 at 08:59:25PM +0800, Haibo Xu wrote: > > > Borrow the csr definitions and operations from kernel's > > > arch/riscv/include/asm/csr.h to tools/ for riscv. > > > > > > Signed-off-by: Haibo Xu <haibo1.xu@intel.com> > > > --- > > > tools/arch/riscv/include/asm/csr.h | 521 +++++++++++++++++++++++++++++ > > > 1 file changed, 521 insertions(+) > > > create mode 100644 tools/arch/riscv/include/asm/csr.h > > > > > > diff --git a/tools/arch/riscv/include/asm/csr.h b/tools/arch/riscv/include/asm/csr.h > > > new file mode 100644 > > > index 000000000000..4e86c82aacbd > > > --- /dev/null > > > +++ b/tools/arch/riscv/include/asm/csr.h > > > @@ -0,0 +1,521 @@ > > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > > +/* > > > + * Copyright (C) 2015 Regents of the University of California > > > + */ > > > + > > > +#ifndef _ASM_RISCV_CSR_H > > > +#define _ASM_RISCV_CSR_H > > > + > > > +#include <linux/bits.h> > > > + > > > +/* Status register flags */ > > > +#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ > > > +#define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */ > > > +#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ > > > +#define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */ > > > +#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ > > > +#define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ > > > +#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ > > > + > > > +#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ > > > +#define SR_FS_OFF _AC(0x00000000, UL) > > > +#define SR_FS_INITIAL _AC(0x00002000, UL) > > > +#define SR_FS_CLEAN _AC(0x00004000, UL) > > > +#define SR_FS_DIRTY _AC(0x00006000, UL) > > > + > > > +#define SR_VS _AC(0x00000600, UL) /* Vector Status */ > > > +#define SR_VS_OFF _AC(0x00000000, UL) > > > +#define SR_VS_INITIAL _AC(0x00000200, UL) > > > +#define SR_VS_CLEAN _AC(0x00000400, UL) > > > +#define SR_VS_DIRTY _AC(0x00000600, UL) > > > + > > > +#define SR_XS _AC(0x00018000, UL) /* Extension Status */ > > > +#define SR_XS_OFF _AC(0x00000000, UL) > > > +#define SR_XS_INITIAL _AC(0x00008000, UL) > > > +#define SR_XS_CLEAN _AC(0x00010000, UL) > > > +#define SR_XS_DIRTY _AC(0x00018000, UL) > > > + > > > +#define SR_FS_VS (SR_FS | SR_VS) /* Vector and Floating-Point Unit */ > > > + > > > +#ifndef CONFIG_64BIT > > > > How do we ensure CONFIG_64BIT is set? > > > > Currently, no explicit checking for this. > Shall we add a gatekeeper in this file to ensure it is set?
Not in this file, since this file is shared by all the tools and...
> > #ifndef CONFIG_64BIT > #error "CONFIG_64BIT was not set" > #endif
...we'll surely hit this error right now since nothing is setting CONFIG_64BIT when compiling KVM selftests.
We need to define CONFIG_64BIT in the build somewhere prior to any headers which depend on it being included. Maybe we can simply add -DCONFIG_64BIT to CFLAGS, since all KVM selftests supported architectures are 64-bit.
(Please trim emails, as I've been doing, when discussing specific parts.)
Thanks, drew
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