Messages in this thread Patch in this message | | | From | Lorenzo Pieralisi <> | Subject | [PATCH 1/2] dt-bindings: interrupt-controller: arm,gic-v3: Add dma-noncoherent property | Date | Tue, 5 Sep 2023 12:47:20 +0200 |
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The GIC v3 specifications allow redistributors and ITSes interconnect ports used to access memory to be wired up in a way that makes the respective initiators/memory observers non-coherent.
Add the standard dma-noncoherent property to the GICv3 bindings to allow firmware to describe the redistributors/ITSes components and interconnect ports behaviour in system designs where the redistributors and ITSes are not coherent with the CPU.
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Cc: Rob Herring <robh@kernel.org> --- .../bindings/interrupt-controller/arm,gic-v3.yaml | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml index 39e64c7f6360..0a81ae4519a6 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml @@ -106,6 +106,10 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 maximum: 4096 + dma-noncoherent: + description: | + Present if the GIC redistributors are not cache coherent with the CPU. + msi-controller: description: Only present if the Message Based Interrupt functionality is @@ -193,6 +197,10 @@ patternProperties: compatible: const: arm,gic-v3-its + dma-noncoherent: + description: | + Present if the GIC ITS is not cache coherent with the CPU. + msi-controller: true "#msi-cells": -- 2.34.1
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