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    Subject[PATCH V4 4/4] dt-bindings: ufs: qcom: Align clk binding property for Qualcomm UFS
    Date
    Align the binding property for clock such that "clocks" property
    comes first followed by "clock-names" property.

    Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
    Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
    ---
    .../devicetree/bindings/ufs/qcom,ufs.yaml | 16 ++++++++--------
    1 file changed, 8 insertions(+), 8 deletions(-)

    diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
    index 802640efa956..d17bdc4e934f 100644
    --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
    +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
    @@ -295,14 +295,6 @@ examples:
    <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
    interconnect-names = "ufs-ddr", "cpu-ufs";

    - clock-names = "core_clk",
    - "bus_aggr_clk",
    - "iface_clk",
    - "core_clk_unipro",
    - "ref_clk",
    - "tx_lane0_sync_clk",
    - "rx_lane0_sync_clk",
    - "rx_lane1_sync_clk";
    clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
    <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
    <&gcc GCC_UFS_PHY_AHB_CLK>,
    @@ -311,6 +303,14 @@ examples:
    <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
    <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
    <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
    + clock-names = "core_clk",
    + "bus_aggr_clk",
    + "iface_clk",
    + "core_clk_unipro",
    + "ref_clk",
    + "tx_lane0_sync_clk",
    + "rx_lane0_sync_clk",
    + "rx_lane1_sync_clk";
    freq-table-hz = <75000000 300000000>,
    <0 0>,
    <0 0>,
    --
    2.17.1
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