Messages in this thread | | | From | Miguel Luis <> | Subject | Re: [PATCH 2/3] arm64/kvm: Fine grain _EL2 system registers list that affect nested virtualization | Date | Tue, 19 Sep 2023 14:54:53 +0000 |
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Hi Marc,
> On 18 Sep 2023, at 09:40, Marc Zyngier <maz@kernel.org> wrote: > > Hi Miguel, > > On Wed, 13 Sep 2023 19:52:07 +0100, > Miguel Luis <miguel.luis@oracle.com> wrote: >> >> Some _EL1 registers got included in the _EL2 ranges, which are not >> affected by NV. Remove them and fine grain the ranges to exclusively >> include the _EL2 ones. >> >> Signed-off-by: Miguel Luis <miguel.luis@oracle.com> >> --- >> arch/arm64/kvm/emulate-nested.c | 44 ++++++++++++++++++++++++++++----- >> 1 file changed, 38 insertions(+), 6 deletions(-) >> >> diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c >> index 9ced1bf0c2b7..9aa1c06abdb7 100644 >> --- a/arch/arm64/kvm/emulate-nested.c >> +++ b/arch/arm64/kvm/emulate-nested.c >> @@ -649,14 +649,46 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = { >> SR_TRAP(SYS_APGAKEYHI_EL1, CGT_HCR_APK), >> /* All _EL2 registers */ >> SR_RANGE_TRAP(sys_reg(3, 4, 0, 0, 0), >> - sys_reg(3, 4, 3, 15, 7), CGT_HCR_NV), >> + sys_reg(3, 4, 4, 0, 1), CGT_HCR_NV), > > It would be good if the commit message explained that you are folding > SPSR/ELR into the existing range. Also, please keep the two ends of > the ranges vertically aligned. >
OK.
>> /* Skip the SP_EL1 encoding... */ >> - SR_TRAP(SYS_SPSR_EL2, CGT_HCR_NV), >> - SR_TRAP(SYS_ELR_EL2, CGT_HCR_NV), >> - SR_RANGE_TRAP(sys_reg(3, 4, 4, 1, 1), >> - sys_reg(3, 4, 10, 15, 7), CGT_HCR_NV), >> + SR_RANGE_TRAP(sys_reg(3, 4, 4, 3, 0), >> + sys_reg(3, 4, 10, 6, 7), CGT_HCR_NV), >> + /* skip MECID_A0_EL2, MECID_A1_EL2, MECID_P0_EL2, >> + * MECID_P1_EL2, MECIDR_EL2, VMECID_A_EL2, >> + * VMECID_P_EL2. >> + */ > > Please follow the kernel comment format. Also, why are you skipping > the MEC registers, but not the MPAM ones? At least indicate a > rationale for this. >
I’m not aware of any exceptions for MPAM registers, although there are for MEC when HCR_EL2.NV2 is 0.
>> SR_RANGE_TRAP(sys_reg(3, 4, 12, 0, 0), >> - sys_reg(3, 4, 14, 15, 7), CGT_HCR_NV), >> + sys_reg(3, 4, 12, 1, 1), CGT_HCR_NV), >> + /* ICH_AP0R<m>_EL2 */ >> + SR_RANGE_TRAP(SYS_ICH_AP0R0_EL2, >> + SYS_ICH_AP0R3_EL2, CGT_HCR_NV), >> + /* ICH_AP1R<m>_EL2 */ >> + SR_RANGE_TRAP(SYS_ICH_AP1R0_EL2, >> + SYS_ICH_AP1R3_EL2, CGT_HCR_NV), >> + SR_RANGE_TRAP(sys_reg(3, 4, 12, 9, 5), >> + sys_reg(3, 4, 12, 11, 7), CGT_HCR_NV), >> + /* ICH_LR<m>_EL2 */ >> + SR_TRAP(SYS_ICH_LR0_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_ICH_LR1_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_ICH_LR2_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_ICH_LR3_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_ICH_LR4_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_ICH_LR5_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_ICH_LR6_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_ICH_LR7_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_ICH_LR8_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_ICH_LR9_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_ICH_LR10_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_ICH_LR11_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_ICH_LR12_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_ICH_LR13_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_ICH_LR14_EL2, CGT_HCR_NV), >> + SR_TRAP(SYS_ICH_LR15_EL2, CGT_HCR_NV), > > You could describe all the LRs a single range. >
Should we skip the gap between LR7 - LR8 ?
>> + SR_RANGE_TRAP(sys_reg(3, 4, 13, 0, 1), >> + sys_reg(3, 4, 13, 0, 7), CGT_HCR_NV), >> + /* skip AMEVCNTVOFF0<n>_EL2 and AMEVCNTVOFF1<n>_EL2 */ > > Why?
I didn’t find its definition TBH although these could use a single range.
Thanks,
Miguel
> >> + SR_RANGE_TRAP(sys_reg(3, 4, 14, 0, 3), >> + sys_reg(3, 4, 14, 5, 2), CGT_HCR_NV), >> /* All _EL02, _EL12 registers */ >> SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0), >> sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV), > > Thanks, > > M. > > -- > Without deviation from the norm, progress is not possible.
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