Messages in this thread | | | Date | Mon, 18 Sep 2023 11:17:46 +0100 | From | Marc Zyngier <> | Subject | Re: [PATCH 2/2] arm64: errata: Add Cortex-A520 speculative unprivileged load workaround |
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On 2023-09-18 11:01, Will Deacon wrote: > On Tue, Sep 12, 2023 at 07:11:15AM -0500, Rob Herring wrote: >> Implement the workaround for ARM Cortex-A520 erratum 2966298. On an >> affected Cortex-A520 core, a speculatively executed unprivileged load >> might leak data from a privileged level via a cache side channel. >> >> The workaround is to execute a TLBI before returning to EL0. A >> non-shareable TLBI to any address is sufficient. > > Can you elaborate at all on how this works, please? A TLBI addressing a > cache side channel feels weird (or is "cache" referring to some TLB > structures rather than e.g. the data cache here?). > > Assuming there's some vulnerable window between the speculative > unprivileged load and the completion of the TLBI, what prevents another > CPU from observing the side-channel during that time? Also, does the > TLBI need to be using the same ASID as the unprivileged load? If so, > then > a context-switch could widen the vulnerable window quite significantly.
Another 'interesting' case is the KVM world switch. If EL0 is affected, what about EL1? Can such a data leak exist cross-EL1, or from EL2 to El1? Asking for a friend...
M. -- Who you jivin' with that Cosmik Debris?
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