Messages in this thread Patch in this message | | | From | Ilpo Järvinen <> | Subject | [PATCH 1/7] PCI: Add PCI_L1SS_CTL2 fields | Date | Fri, 15 Sep 2023 18:57:46 +0300 |
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Add L1 PM Substates Control 2 Register fields (PCI_L1SS_CTL2_*).
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> --- include/uapi/linux/pci_regs.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index e5f558d96493..3a7ea9581568 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1088,6 +1088,8 @@ #define PCI_L1SS_CTL1_LTR_L12_TH_VALUE 0x03ff0000 /* LTR_L1.2_THRESHOLD_Value */ #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ +#define PCI_L1SS_CTL2_T_PWR_ON_SCALE 0x00000003 /* T_POWER_ON Scale */ +#define PCI_L1SS_CTL2_T_PWR_ON_VALUE 0x000000f8 /* T_POWER_ON Value */ /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ #define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */ -- 2.30.2
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