Messages in this thread | | | Date | Fri, 15 Sep 2023 15:11:43 +0100 | From | Conor Dooley <> | Subject | Re: [PATCH 04/12] dt-bindings: riscv: Add T-HEAD C920 compatibles |
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On Fri, Sep 15, 2023 at 03:23:33PM +0800, Wang Chen wrote: > The C920 is RISC-V CPU cores from T-HEAD Semiconductor. > Notably, the C920 core is used in the SOPHGO SG2042 SoC. > > Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn> > Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
I figure this is missing a From: or Co-developed-by line.
> --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 38c0b5213736..185a0191bad6 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -47,6 +47,7 @@ properties: > - sifive,u74-mc > - thead,c906 > - thead,c910 > + - thead,c920 > - const: riscv > - items: > - enum: > -- > 2.25.1 > [unhandled content-type:application/pgp-signature] | |