Messages in this thread | | | Date | Mon, 11 Sep 2023 10:38:28 +0200 | Subject | Re: [PATCH v2 1/2] drm/amd/display: fix the white screen issue when >= 64GB DRAM | From | Christian König <> |
| |
Am 08.09.23 um 16:55 schrieb Hamza Mahfooz: > From: Yifan Zhang <yifan1.zhang@amd.com> > > Dropping bit 31:4 of page table base is wrong, it makes page table > base points to wrong address if phys addr is beyond 64GB; dropping > page_table_start/end bit 31:4 is unnecessary since dcn20_vmid_setup > will do that. Also, while we are at it, cleanup the assignments using > upper_32_bits()/lower_32_bits() and AMDGPU_GPU_PAGE_SHIFT. > > Cc: stable@vger.kernel.org > Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2354 > Fixes: 81d0bcf99009 ("drm/amdgpu: make display pinning more flexible (v2)") > Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> > Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com> for the series as well.
> --- > v2: use upper_32_bits()/lower_32_bits() and AMDGPU_GPU_PAGE_SHIFT > --- > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 +++++++++----- > 1 file changed, 9 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > index 1bb1a394f55f..5f14cd9391ca 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > @@ -1283,11 +1283,15 @@ static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_ > > pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); > > - page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF; > - page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12); > - page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF; > - page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12); > - page_table_base.high_part = upper_32_bits(pt_base) & 0xF; > + page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >> > + AMDGPU_GPU_PAGE_SHIFT); > + page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >> > + AMDGPU_GPU_PAGE_SHIFT); > + page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >> > + AMDGPU_GPU_PAGE_SHIFT); > + page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >> > + AMDGPU_GPU_PAGE_SHIFT); > + page_table_base.high_part = upper_32_bits(pt_base); > page_table_base.low_part = lower_32_bits(pt_base); > > pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
| |